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december 2009 i ? 2010 actel corporation automotive proasic3 flash family fpgas features and benefits high-temperature aec-q100?qualified devices ? grade 2 105c t a (115c t j ) ? grade 1 125c t a (135c t j ) ? ppap documentation firm-error immune ? only automotive fpgas to offer firm-error immunity ? can be used without configuration upset risk high capacity ? 60 k to 1 m system gates ? up to 144 kbits of sram ? up to 300 user i/os reprogrammable flash technology ? 130-nm, 7-layer metal (6 copper), flash-based cmos automotive process ? live-at-power-up (lapu) level 0 support ? single-chip solution ? retains programmed design when powered off on-chip user nonvolatile memory ? 1 kbit of flashrom with synchronous interface high performance ? 350 mhz system performance ? 3.3 v, 66 mhz 64-bit pci in-system programming (isp) and security ? secure isp using on-chip 128-bit advanced encryption standard (aes) decryption via jtag (ieee 1532?compliant) ? flashlock ? to secure fpga contents (anti-tampering) low power ? 1.5 v core voltage ? support for 1.5-v-only systems ? low-impedance flash switches high-performance routing hierarchy ? segmented, hierarchical routing and clock structure ? high-performance, low-skew global network ? architecture supports ultra-high utilization advanced i/o ? 700 mbps ddr, lvds-capable i/os ? 1.5 v, 1.8 v, 2.5 v, and 3.3 v mixed-voltage operation ? bank-selectable i/o voltages?up to 4 banks per chip ? single-ended i/o standards: lvttl, lvcmos 3.3 v / 2.5 v / 1.8 v / 1.5 v, 3.3 v pci / 3.3 v pci-x, and lvcmos 2.5 v / 5.0 v input ? differential i/o standards: lvpecl, lvds, b-lvds, and m-lvds (a3p250 and a3p1000) ? i/o registers on input, output, and enable paths ? hot-swappable and cold-sparing i/os ? programmable output slew rate and drive strength ? weak pull-up/-down ? ieee 1149.1 (jtag) boundary scan test ? pin-compatible packages across the automotive proasic ? 3 family clock conditioning circuit (ccc) and pll ? six ccc blocks, one with an integrated pll ? configurable phase shift, multiply/divide, delay capabilities, and external feedback ? wide input frequency range (1.5 mhz up to 350 mhz) srams ? variable-aspect-ratio 4,608-bit ram blocks (1, 2, 4, 9, and 18 organizations available) table 1 ? automotive proasic3 product family proasic3 devices a3p060 a3p125 a3p250 a3p1000 system gates 60 k 125 k 250 k 1 m versatiles (d-flip-flops ) 1,536 3,072 6,144 24,576 ram kbits (1,024 bits) 18 36 36 144 4,608-bit blocks 4 8 8 32 flashrom bits 1 k 1 k 1 k 1 k secure (aes) isp yes yes yes yes integrated pll in cccs1111 versanet globals1 18 18 18 18 i/o banks 2244 maximum user i/os 96 133 157 300 package pins vqfp fbga qfn 2 vq100 fg144 vq100 fg144 qng132 vq100 fg144, fg256 qng132 fg144, fg256, fg484 notes: 1. six chip-wide (main) globals and three additional global networks in each quadrant are available. 2. qfn packages are available as rohs compliant only. revision 1 ?
proasic3 nano flash fpgas ii revision 1 i/os per package automotive proasic3 device status proasic3 devices a3p060 a3p125 a3p250 a3p1000 package i/o type single-ended i/o single-ended i/o single-ended i/o 2 differential i/o pairs single-ended i/o 2 differential i/o pairs vq100 71716813 ? ? fg144 969797249725 fg256 ? ? 157 38 177 44 fg484 ? ? ? ? 300 74 qng132 ? 84 87 19 ? ? notes: 1. when considering migrating your design to a lower- or higher-density device, refer to the proasic3 fpga fabric user?s guide to ensure complying with design and board migration requirements. 2. each used differential i/o pair reduces the number of available single-ended i/os by two. 3. fg256 and fg484 are footprint-compatible packages. automotive proasic3 devices status a3p060 production a3p125 production a3p250 production a3p1000 production
automotive proasic3 flash family fpgas revision 1 iii automotive proasic3 ordering information note: minimum order quantities apply. contact yo ur local actel sales office for details. speed grade blank = standard 1 = 15% faster than standard a3p1000 fg _ part number automotive proasic3 devices 1 package type vq = very thin quad flat pack (0.5 mm pitch) 144 t package lead count lead-free packaging application (temperature range) t = grade 2 and grade 1 aecq100 grade 2 = 105c t a and 115c t j blank = standard packaging grade 1 = 125c t a and 135c t j 60,000 system gates a3p060 = 125,000 system gates a3p125 = 250,000 system gates a3p250 = 1,000,000 system gates a3p1000 = fg = fine pitch ball grid array (1.0 mm pitch) qn = quad flat pack (0.5 mm pitch) g = rohs-compliant (green) packaging g
proasic3 nano flash fpgas iv revision 1 temperature grade offerings speed grade and temperature grade matrix contact your local actel representative for device availability: http://www.actel.com /contact/default.aspx . package a3p060 a3p125 a3p250 a3p1000 vq100 c, i, t c, i, t c, i, t ? fg144 c, i, t c, i, t c, i, t c, i, t fg256 ? ? c, i, t c, i, t fg484 ? ? ? c, i, t qng132 ? c, i, t c, i, t ? notes: 1. c = commercial temperature range: 0c to 70c 2. i = industrial temperature range: ?40c to 85c 3. t = automotive temperature range: grade 2 and grade 1 aec-q100 grade 2 = 105c t a and 115c t j grade 1 = 125c t a and 135c t j 4. specifications for commercial and indu strial grade devices can be found in the proasic3 flash family fpgas datasheet. temperature grade std. ?1 t (grade 1 and grade 2), commercial, industrial ?? notes: 1. t = automotive temperature range: grade 2 and grade 1 aec-q100 grade 2 = 105c t a and 115c t j grade 1 = 125c t a and 135c t j 2. specifications for commercial and indu strial grade devices can be found in the proasic3 flash family fpgas datasheet.
automotive proasic3 flash family fpgas revision 1 v table of contents automotive proasic3 de vice family overview general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 automotive proasic3 dc and switching characteristics general specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 calculating power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6 user i/o characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-12 versatile characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-69 global resource characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-75 clock conditioning circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-80 embedded sram and fifo characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-82 embedded flashrom characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-97 jtag 1532 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-98 package pin assignments 100-pin vqfp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 132-pin qfn . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4 144-pin fbga . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9 256-pin fbga . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-18 484-pin fbga . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-25 datasheet information list of changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 datasheet categories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2 actel safety critical, life support, and high-reliability applications policy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2

revision 1 1-1 1 ? automotive proasic3 device family overview general description automotive proasic3 nonvolatile flash technology gives automotive system designers the advantage of a secure, low-power, single-chip solution that is live at power-up (lapu). automotive proasic3 is reprogrammable and offers time-to -market benefits at an asic-level unit cost. these features enable designers to create high-density systems using ex isting asic or fpga design flows and tools. automotive proasic3 devices offer 1 kbit of on-c hip, reprogrammable, nonvol atile flashrom storage as well as clock conditioning circuitry based on an integrated phase-locked loop (pll). automotive proasic3 devices have up to 1 million system gate s, supported with up to 144 kbits of sram and up to 300 user i/os. automotive proasic3 devices are the only fir m-error-immune automotive grade fpgas. firm-error immunity makes them ideally suited for demanding applications in powertrain, safety, and telematics- based subsystems, where firm-error failure is not an option. firm errors in sram-based fpgas can result in high defect levels in fi eld-deployed systems. these unavoidable defects must be considered separately from standard defects and failure mechanisms when looking at overall system quality and reliability. flash advantages reduced cost of ownership advantages to the designer extend beyond low unit cost, performance, and ease of use. unlike sram- based fpgas, flash-based automotive proasic3 devi ces allow all functionality to be live at power-up; no external boot prom is required. on-board se curity mechanisms prevent access to all the programming information and enable secure remote upd ates of the fpga logic. flash-based fpgas are lapu class 0 devices, offering the lowest availabl e power in a single-chip device and providing firm- error immunity. the automotive proasic3 family device architecture mitigates the need for asic migration at high user volumes. this makes the automotive proasic3 fami ly a cost-effective asic replacement solution, especially for automotive applications. security the nonvolatile, flash-based automotive proasic3 dev ices do not require a boot prom, so there is no vulnerable external bitstream that can be easily copied. automotive proasi c3 devices incorporate flashlock, which provides a unique combination of reprogrammability and design security without external overhead, advantages that only an fpga with nonvolatile flash programming can offer. automotive proasic3 dev ices utilize a 128-bit flash-based lock and a se parate aes key to secure programmed intellectual property and configuration data. in addition, all flashrom data in automotive proasic3 devices can be encrypted prior to loading, using the indus try-leading aes-128 (fips192) bit block cipher encryption standard. the aes was adop ted by the national institute of standards and technology (nist) in 2000 and replaces the 1977 des standard. automotive proasic3 devices have a built-in aes decryption engine and a flash-based aes key that make them the most comprehensive programmable logic device security solution available to day. automotive proasi c3 devices with aes- based security allow for secure, remote field upda tes over public networks such as the internet, and ensure that valuable ip remains out of the hands of system overbuilders, system cloners, and ip thieves. the contents of a programmed automotive pro asic3 device cannot be read back, although secure design verification is possible. additionally, security features of automotive proasic3 devices provide anti-tampering protection. security, built into the fpga fabric, is an inherent component of the automoti ve proasic3 family. the flash cells are located beneath seven metal layers , and many device design and layout techniques have been used to make invasive attacks ex tremely difficult. the automotive proasic3 family, with flashlock and aes security, is unique in being highly resistan t to both invasive and noninvasive attacks. your
automotive proasic3 de vice family overview 1-2 revision 1 valuable ip is protected and secu re. an automotive proasic3 devic e provides the most impenetrable security for programmable logic designs. single chip flash-based fpgas store their configuration informati on in on-chip flash cells. once programmed, the configuration data is an inherent part of the fpga st ructure, and no external configuration data needs to be loaded at system power-up (unlike sram-based fpgas). therefore, flash-based automotive proasic3 fpgas do not require system conf iguration components such as eeproms or microcontrollers to load device configuration data. this reduces bill-of-materials costs and pcb area, and increases security and system reliability. live at power-up the actel flash-based automotive proasic3 devices support level 0 of the lapu classification standard. this feature helps in system component in itialization, execution of critical tasks before the processor wakes up, setup and conf iguration of memory blocks, cl ock generation, and bus activity management. the lapu feature of fl ash-based automotive proasic3 devices greatly simplifies total system design and reduces total system cost, often eliminating the need for cplds and external clock generation plls. in additi on, glitches and brownouts in system power will not corrupt the automotive proasic3 device's flash configurat ion, and unlike sram-based fpgas, the device will not have to be reloaded when system power is restored. this enabl es the reduction or complete removal of the configuration prom, expensive voltage monitor, br ownout detection, and clock generator devices from the pcb design. flash-based automotive proasic3 devices simplify tota l system design and reduce cost and design risk while increasing system re liability and improving system initialization time. firm-error immunity firm errors occur most commonly when high-energy neutrons, generated in the upper atmosphere, strike a configuration cell of an sram fpga. the energ y of the collision can ch ange the state of the configuration cell and thus change t he logic, routing, or i/o behavior in an unpredictable way. these errors are impossible to prevent in sram fpgas. the consequence of this type of error can be a complete system failure. firm errors do not exist in the configuratio n memory of automotive proasic3 flash-based fpgas. once it is programmed, the flas h cell configuration element of automotive proasic3 fpgas cannot be altered by high-energy neutrons and is therefore immune to them. recoverable (or soft) errors occur in the user data sram of all fp ga devices. these can easily be mitigated by using error detection and correction (edac) ci rcuitry built into the fpga fabric. low power flash-based automotive proasic3 dev ices exhibit very low power characteristics, similar to those of an asic, making them an ideal choice for power-sensiti ve applications. automoti ve proasic3 devices have only a very limited power-on current surge and no high-c urrent transition period, both of which occur on many fpgas. automotive proasic3 devi ces also have low dynami c power consumption to further maximize power savings. advanced flash technology the automotive proasic3 family offers many be nefits, including nonvolat ility and reprogrammability, through an advanced flash-based, 130-nm lvcmos process with se ven layers of metal. standard cmos design techniques are used to implement logi c and control functions. the combination of fine granularity, enhanced flexible routing resources, a nd abundant flash switches allows for very high logic utilization without compromising device routability or performance. logic functions within the device are interconnected through a four-level routing hierarchy.
automotive proasic3 flash family fpgas revision 1 1-3 advanced architecture the proprietary automotive proasic3 architecture provides granularity comparable to standard-cell asics. the automotive proasic3 dev ice consists of five distinct and programmable architectural features ( figure 1-1 and figure 1-2 on page 1-4 ): ? fpga versatiles ? dedicated flashrom ? dedicated sram memory ? extensive cccs and plls ? advanced i/o structure the fpga core consists of a sea of versatiles. each versatile can be configured as a three-input logic function, a d-flip-flop (with or without enable), or a latch by progr amming the appropriate flash switch interconnections. the versatility of the automotive pro asic3 core tile as either a three-input lookup table (lut) equivalent or a d-flip-flop/latch with enable allows for efficient use of the fpga fabric. the versatile capability is unique to the actel proasic family of third-generation- architecture flash fpgas. versatiles are connected with any of the four levels of routing hierarchy. flash switches are distributed throughout the device to provide nonvolatile, re configurable interconnect programming. maximum core utilization is possible for virtually any design. in addition, extensive on-chip programming circuitry allows for rapid, single-voltage (3.3 v) programming of automotive proasi c3 devices via an ieee 1532 jtag interface. figure 1-1 ? automotive proasic3 device architecture ov erview with two i/o banks (a3p060 and a3p125) ram block 4,608-bit sram or fifo block versatile ccc i/os isp aes decryption user nonvolatile flashrom charge pumps bank 0 bank 1 bank 1 bank 0 bank 0 bank 1
automotive proasic3 de vice family overview 1-4 revision 1 versatiles the automotive proasic3 core consists of versatiles, which have been enhanced beyond the proasic plus ? core tiles. the automotive proasic3 versatile supports the following: ? all 3-input logic functions?lut-3 equivalent ? latch with clear or set ? d-flip-flop with clear or set ? enable d-flip-flop with clear or set refer to figure 1-3 for versatile configurations. figure 1-2 ? automotive proasic3 device architecture overview with four i/o banks (a3p600 and a3p1000) ram block 4,608-bit sram or fifo block (a3p600 and a3p1000) ram block 4,608-bit sram or fifo block versatile ccc i/os isp aes decryption user nonvolatile flashrom charge pumps bank 0 bank 3 bank 3 bank 1 bank 1 bank 2 figure 1-3 ? versatile configurations x1 y x2 x3 lut-3 data y clk enable clr d-ff data y clk clr d-ff lut-3 equivalent d-flip-flop with clear or set enable d-flip-flop with clear or set
automotive proasic3 flash family fpgas revision 1 1-5 user nonvolatile flashrom actel automotive proasic3 devices have 1 kbit of on-chip, user-accessible, nonvolatile flashrom. the flashrom can be used in diverse system applications: ? unique protocol addressing (wireless or fixed) ? system calibration settings ? device serialization and/or inventory control ? subscription-based business models (for example, in fotainment systems) ? secure key storage for secure communications algorithms ? asset management/tracking ? date stamping ? version management the flashrom is written using the standard au tomotive proasic3 ieee 1532 jtag programming interface. the flashrom can be programmed via the jtag progr amming interface, and its contents can be read back either through the jtag programming interface or via direct fpga core addressing. note that the flashrom can only be programmed from the jtag interface and cannot be programmed from the internal logic array. the flashrom is programmed as 8 banks of 128 bits ; however, reading is performed on a byte-by-byte basis using a synchronous interface. a 7-bit address fr om the fpga core defines which of the 8 banks and which of the 16 bytes within that bank are being read. the three most significant bits (msbs) of the flashrom address determine the bank, and the four least significant bits (lsbs) of the flashrom address define the byte. the actel automotive proasic3 development software solutions, libero ? integrated design environment (ide) and designer, have extensive suppo rt for the flashrom. on e such feature is auto- generation of sequential programming files for applications requiring a unique serial number in each part. another feature allo ws the inclusion of static da ta for system version control. data for the flashrom can be generated quickly and easily using actel libero ide and designer software tools. comprehensive programming file support is also included to allow for easy programming of large numbers of parts with differing flashrom contents. sram automotive proasic3 devices have embedded sram blocks along their north and south sides. each variable-aspect-ratio sram block is 4,608 bits in size. available memory configurations are 25618, 5129, 1k4, 2k2, and 4k1 bits. the individual bl ocks have independent read and write ports that can be configured with different bit widths on each port. for example, data can be sent through a 4-bit port and read as a single bitstream. the embedded sram blocks can be initializ ed via the device jtag port (rom emulation mode) using the ujtag macro. pll and ccc automotive proasic3 devices provide designers wit h very flexible clock conditioning circuit (ccc) capabilities. each member of the automotive pr oasic3 family contains six cccs. one ccc (center west side) has a pll. the six ccc blocks are locate d at the four corners an d the centers of the east and west sides. one ccc (center west side) has a pll. all six ccc blocks are usable; the four corner cccs and the east ccc allo w simple clock delay operations as well as clock spine access. the inputs of the six ccc blocks are accessible from the fpga core or from one of several inputs located near the ccc that have dedicated connections to the ccc block. the ccc block has these key features: ? wide input frequency range (f in_ccc ) = 1.5 mhz to 350 mhz ? output frequency range (f out_ccc ) = 0.75 mhz to 350 mhz ? clock delay adjustment via programmable a nd fixed delays from ?7.56 ns to +11.12 ns ? 2 programmable delay types for clock skew minimization
automotive proasic3 de vice family overview 1-6 revision 1 ? clock frequency synthesis (for pll only) additional ccc specifications: ? internal phase shift = 0, 90, 180, and 270. output phase shift depends on the output divider configuration (for pll only). ? output duty cycle = 50% 1.5% or better (for pll only) ? low output jitter: worst case < 2.5% clock per iod peak-to-peak period jitter when single global network used (for pll only) ? maximum acquisition time is 300 s (for pll only) ? low power consumption of 5 mw ? exceptional tolerance to input period jitter? allowa ble input jitter is up to 1.5 ns (for pll only) ? four precise phases; maximum misalignment bet ween adjacent phases of 40 ps 350 mhz / f out_ccc (for pll only) global clocking automotive proasic3 devices have extensive support for multiple clocking domains. in addition to the ccc and pll support described above, there is a co mprehensive global clock distribution network. each versatile input and output port has access to nine versanets: six chip (main) and three quadrant global networks. the versanets can be driven by the ccc or directly accessed from the core via multiplexers (muxes). the versanets can be used to distribute low-skew clock signals or for rapid distribution of high-fanout nets. i/os with advanced i/o standards the automotive proasic3 family of fpgas features a flexible i/o structure, supporting a range of voltages (1.5 v, 1.8 v, 2.5 v, and 3.3 v). automotive proasic3 fpgas support many different i/o standards?single-ended and differential. the i/os are organized into banks, with two or four banks per device. the configuration of these banks determines the i/o standards supported. each i/o module contains several input, output, and enable registers. these registers allow the implementation of the following: ? single-data-rate applications ? double-data-rate applications?ddr lvds, b-lvds, and m-lvds i/os for point-to-point communications automotive proasic3 banks for the a3p250 and a3p1000 devices support lvpecl, lvds, b-lvds, and m-lvds. b-lvds and m-lvds can support up to 20 loads.
revision 1 2-1 2 ? automotive proasic3 dc and switching characteristics general specifications operating conditions stresses beyond those listed in ta b l e 2 - 1 may cause permanent damage to the device. exposure to absolute maximum rating conditions for extended periods may affect device reliability. absolute maximums are stress ratings only; functi onal operation of the devic e at these or any other conditions beyond those listed under the reco mmended operating conditions specified in ta b l e 2 - 2 o n page 2-2 is not implied. table 2-1 ? absolute maximum ratings symbol parameter limits units vcc dc core supply voltage ?0.3 to 1.65 v vjtag jtag dc voltage ?0.3 to 3.75 v vpump programming voltage ?0.3 to 3.75 v vccpll analog power supply (pll) ?0.3 to 1.65 v vcci dc i/o output buffer supply voltage ?0.3 to 3.75 v vmv dc i/o input buffer supply voltage ?0.3 to 3.75 v vi i/o input voltage ?0.3 v to 3.6 v (when i/o hot insertion mode is enabled) ?0.3 v to (v cci + 1 v) or 3.6 v, whichever voltage is lower (when i/o hot-insertion mode is disabled) v t stg 2 storage temperature ?65 to +150 c t j 2 junction temperature +150 c notes: 1. the device should be operated within the limits specified by the datasheet. during transitions, the input signal may undershoot or overshoot according to the limits shown in table 2-3 on page 2-3 . 2. for flash programming and retention maximum limits, refer to figure 2-1 on page 2-2 . for recommended operating limits, refer to table 2-2 on page 2-2 .
automotive proasic3 dc and switching characteristics 2-2 revision 1 table 2-2 ? recommended operating conditions symbol parameter automotive grade 1 automotive grade 2 unit s t j junction temperature ?40 to +135 ?40 to +115 c vcc 1.5 v dc core supply voltage 1.425 to 1.575 1.425 to 1.575 v vjtag jtag dc voltage 1.4 to 3.6 1.4 to 3.6 v vpump programming voltage programming mode 3.0 to 3.6 3.0 to 3.6 v operation 3 0 to 3.6 0 to 3.6 v vccpll analog power supply (pll) 1.4 to 1.6 1.4 to 1.6 v vcci and vmv 1.5 v dc supply voltage 1.425 to 1.575 1.425 to 1.575 v 1.8 v dc supply voltage 1.7 to 1.9 1.7 to 1.9 v 2.5 v dc supply voltage 2.3 to 2.7 2.3 to 2.7 v 3.3 v dc supply voltage 3.0 to 3.6 3.0 to 3.6 v lvds/b-lvds/m-lvds differential i/o 2.375 to 2.625 2.375 to 2.625 v lvpecl differential i/o 3.0 to 3.6 3.0 to 3.6 v notes: 1. the ranges given here are for power supplies only. th e recommended input voltage ranges specific to each i/o standard are given in table 2-14 on page 2-16 . vmv and v cci should be at the same voltage within a given i/o bank. 2. all parameters representing voltages are measured with respect to gnd unless otherwise specified. 3. v pump can be left floating during operation (not programming mode). note: htr time is the period during which you would not ex pect a verify failure due to flash cell leakage. figure 2-1 ? high-temperature da ta retention (htr) 0 10 20 30 40 50 60 70 80 90 100 110 70 85 100 105 110 115 120 125 130 135 140 145 150 temperature (oc) years tj (c) htr lifetime (yrs) 70 102.7 85 43.8 100 20.0 105 15.6 110 12.3 115 9.7 120 7.7 125 6.2 130 5.0 135 4.0 140 3.3 145 2.7 150 2.2
automotive proasic3 flash family fpgas revision 1 2-3 i/o power-up and supply voltage thresholds for power-on reset (commercial and industrial) sophisticated power-up management circui try is designed into every proasic ? 3 device. these circuits ensure easy transition from the powered-off state to the powered-up state of the device. the many different supplies can power up in any sequence with mi nimized current spikes or surges. in addition, the i/o will be in a known state through the power-up sequence. the basic principle is shown in figure 2-2 on page 2-4 . there are five regions to consider during power-up. proasic3 i/os are activated only if all of the following three conditions are met: 1. vcc and vcci are above the minimum specified trip points ( figure 2-2 on page 2-4 ). 2. vcci > vcc ? 0.75 v (typical) 3. chip is in the operating mode. vcci t rip point: ramping up: 0.6 v < trip_point_up < 1.2 v ramping down: 0.5 v < trip_point_down < 1.1 v vcc trip point: ramping up: 0.6 v < trip_point_up < 1.1 v ramping down: 0.5 v < trip_point_down < 1 v vcc and vcci ramp-up trip points are about 100 mv hi gher than ramp-down trip points. this specifically built-in hysteresis prevents undesirable power-up oscillations and current surges. note the following: ? during programming, i/os become tristated and weakly pulled up to v cci . ? jtag supply, pll power supplies, and charge pump v pump supply have no influence on i/o behavior. internal power-up activation sequence 1. core 2. input buffers 3. output buffers, after 200 ns delay from input buffer activation table 2-3 ? overshoot and undershoot limits (as measured on quiet i/os) vcci and vmv average vcci?gnd overshoot or undershoot duration as a percentage of clock cycle maximum overshoot/ undershoot (115c) maximum overshoot/ undershoot (135c) 2.7 v or less 10% 0.81 v 0.72 v 5% 0.90 v 0.82 v 3 v 10% 0.80 v 0.72 v 5% 0.90 v 0.81 v 3.3 v 10% 0.79 v 0.69 v 5% 0.88 v 0.79 v 3.6 v 10% n/a n/a 5% n/a n/a notes: 1. the duration is allowed at one out of six clock cycles (estimated sso density over cycles). if the overshoot/undershoot occurs at one out of two cycles, the maximum overshoot/undershoot has to be reduced by 0.15 v. 2. this table refers only to overshoot/undershoot limits for simultaneously switching i/os and does not provide pci overshoot/undershoot limits.
automotive proasic3 dc and switching characteristics 2-4 revision 1 thermal characteristics introduction the temperature variable in the actel designer soft ware refers to the junction temperature, not the ambient temperature. this is an important distin ction because dynamic and static power consumption cause the chip junction to be hi gher than the ambi ent temperature. eq 1 can be used to calculate junction temperature. t j = junction temperature = t + t a eq 1 where: t a = ambient temperature t = temperature gradient between junction (silicon) and ambient t = ja * p ja = junction-to-ambient of the package. ja numbers are located in table 2-4 on page 2-5 . p = power dissipation figure 2-2 ? i/o state as a function of vcci and vcc voltage levels region 1: i/o buffers are off region 2: i/o buffers are on. i/os are functional (except differential inputs) but slower because vcci / vcc are below specification. for the same reason, input buffers do not meet vih / vil levels, and output buffers do not meet voh / vol levels. min vcci datasheet specification voltage at a selected i/o standard; i.e., 1.425 v or 1.7 v or 2.3 v or 3.0 v vcc vcc = 1.425 v region 1: i/o buffers are off activation trip point: v a = 0.85 v 0.25 v deactivation trip point: v d = 0.75 v 0.25 v activation trip point: v a = 0.9 v 0.3 v deactivation trip point: v d = 0.8 v 0.3 v vcc = 1.575 v region 5: i/o buffers are on and power supplies are within specification. i/os meet the entire datasheet and timer specifications for speed, vih / vil, voh / vol, etc. region 4: i/o buffers are on. i/os are functional (except differential but slower because vcci is below specification. for the same reason, input buffers do not meet vih / vil levels, and output buffers do not meet voh / vol levels. where vt can be from 0.58 v to 0.9 v (typically 0.75 v) vcci region 3: i/o buffers are on. i/os are functional; i/o dc specifications are met, but i/os are slower because the vcc is below specification. vcc = vcci + vt
automotive proasic3 flash family fpgas revision 1 2-5 package thermal characteristics the device junction-to-case thermal resistivity is jc and the junction-to-ambient air thermal resistivity is ja . the thermal characteristics for ja are shown for two air flow rates. the absolute maximum junction temperature is 110c. eq 2 shows a sample calculation of the absolute maximum power dissipation allowed for a 484-pin fbga package at commercial temperature and in still air. eq 2 temperature and voltage derating factors maximum power allowed max. junction temp. ( c) max. ambient temp. ( c) ? ja ( c/w) ------------------------------------------------------------------------------------------------------------------------------- -------- 110 c70 c ? 20.5c/w ------------------------------------ 1.951 w = = = table 2-4 ? package thermal resistivities package type device pin count jc ja units still air 200 ft./min. 500 ft./min. very thin quad flat pack (vqfp) all devices 100 10.0 35.3 29.4 27.1 c/w fine pitch ball grid array (fbga) see note* 144 3.8 26.9 22.9 21.5 c/w see note* 256 3.8 26.6 22.8 21.5 c/w see note* 484 3.2 20.5 17.0 15.9 c/w a3p1000 144 6.3 31.6 26.2 24.2 c/w a3p1000 256 6.6 28.1 24.4 22.7 c/w a3p1000 484 8.0 23.3 19.0 16.7 c/w * this information applies to all proasic3 devices ex cept the a3p1000. detaile d device/package thermal information will be available in future revisions of the datasheet. table 2-5 ? temperature and voltage derati ng factors for timing delays (normalized to t j = 115c, vcc = 1.425 v) array voltage vcc (v) ?40c 0c 25c 70c 85c 115c 125c 135c 1.425 0.83 0.88 0.90 0. 95 0.97 1.00 1.01 1.02 1.5 0.79 0.83 0.85 0.90 0.92 0.95 0.96 0.97 1.575 0.76 0.80 0.82 0. 87 0.88 0.91 0.93 0.94
automotive proasic3 dc and switching characteristics 2-6 revision 1 calculating power dissipation quiescent supply current power per i/o pin table 2-6 ? quiescent supply current characteristics a3p060 a3p125 a3p250 a3p1000 typical (25c) 2 ma 2 ma 3 ma 8 ma maximum (automotive grade 1) ? 135c 53 ma 53 ma 106 ma 265 ma maximum (automotive grade 2) ? 115c 26 ma 26 ma 53 ma 131 ma note: i dd includes vcc, vpum p, vcci, and vmv currents. va lues do not include i/o static contribution, which is shown in ta ble 2-7 and table 2-10 on page 2-8 . table 2-7 ? summary of i/o input buffe r power (per pin) ? defa ult i/o software settings 1 applicable to advanced i/o banks vmv (v) static power p dc2 (mw) 1 dynamic power p ac9 (w/mhz) 2 single-ended 3.3 v lvttl / 3.3 v lvcmos 3.3 ? 16.69 2.5 v lvcmos 2.5 ? 5.12 1.8 v lvcmos 1.8 ? 2.13 1.5 v lvcmos (jesd8-11) 1.5 ? 1.45 3.3 v pci 3.3 ? 18.11 3.3 v pci-x 3.3 ? 18.11 differential lvds 2.5 2.26 1.20 lvpecl 3.3 5.72 1.87 notes: 1. p dc2 is the static power (where applicable) measured on vmv. 2. p ac9 is the total dynamic power measured on v cc and vmv.
automotive proasic3 flash family fpgas revision 1 2-7 table 2-8 ? summary of i/o input buffe r power (per pin) ? defa ult i/o software settings 1 applicable to standard plus i/o banks vmv (v) static power p dc2 (mw) 1 dynamic power p ac9 (w/mhz) 2 single-ended 3.3 v lvttl / 3.3 v lvcmos 3.3 ? 16.72 2.5 v lvcmos 2.5 ? 5.14 1.8 v lvcmos 1.8 ? 2.13 1.5 v lvcmos (jesd8-11) 1.5 ? 1.48 3.3 v pci 3.3 ? 18.13 3.3 v pci-x 3.3 ? 18.13 notes: 1. p dc2 is the static power (where applicable) measured on vmv. 2. p ac9 is the total dynamic power measured on v cc and vmv. table 2-9 ? summary of i/o output bu ffer power (per pin) ? de fault i/o softw are settings 1 applicable to advanced i/o banks c load (pf) vcci (v) static power p dc3 (mw) 2 dynamic power p ac10 (w/mhz) 3 single-ended 3.3 v lvttl / 3.3 v lvcmos 35 3.3 ? 468.67 2.5 v lvcmos 35 2.5 ? 267.48 1.8 v lvcmos 35 1.8 ? 149.46 1.5 v lvcmos (jesd8-11) 35 1.5 ? 103.12 3.3 v pci 10 3.3 ? 201.02 3.3 v pci-x 10 3.3 ? 201.02 differential lvds ? 2.5 7.74 88.92 lvpecl ? 3.3 19.54 166.52 notes: 1. dynamic power consumption is given for standard load and software default drive strength and output slew. 2. p dc3 is the static power (where applicable) measured on vmv. 3. p ac10 is the total dynamic power measured on v cci and vmv.
automotive proasic3 dc and switching characteristics 2-8 revision 1 table 2-10 ? summary of i/o output bu ffer power (per pin) ? de fault i/o softw are settings 1 applicable to standard plus i/o banks c load (pf) vcci (v) static power p dc3 (mw) 2 dynamic power p ac10 (w/mhz) 3 single-ended 3.3 v lvttl / 3.3 v lvcmos 35 3.3 ? 452.67 2.5 v lvcmos 35 2.5 ? 258.32 1.8 v lvcmos 35 1.8 ? 133.59 1.5 v lvcmos (jesd8-11) 35 1.5 ? 92.84 3.3 v pci 10 3.3 ? 184.92 3.3 v pci-x 10 3.3 ? 184.92 notes: 1. dynamic power consumption is given for standard load and software default drive strength and output slew. 2. p dc3 is the static power (where applicable) measured on vmv. 3. p ac10 is the total dynamic power measured on v cci and vmv.
automotive proasic3 flash family fpgas revision 1 2-9 power consumption of vari ous internal resources power calculation methodology this section describes a simplified method to estima te power consumption of an application. for more accurate and detailed power estimations, use the smartpower tool in actel libero ide software. the power calculation methodology described below uses the following variables: ? the number of plls as well as the number a nd the frequency of each output clock generated ? the number of combinatorial and sequential cells used in the design ? the internal clock frequencies ? the number and the standard of i/o pins used in the design ? the number of ram blocks used in the design ? toggle rates of i/o pins as well as versatiles?guidelines are provided in table 2-12 on page 2-11 . ? enable rates of output buffers?guidelines are provided for typical applications in table 2-13 on page 2-12 . ? read rate and write rate to the memory?guidel ines are provided for typical applications in table 2-13 on page 2-12 . the calculation should be repeated for each clock domain defined in the design. methodology total power consumption?p total p total = p stat + p dyn p stat is the total static power consumption. p dyn is the total dynamic power consumption. table 2-11 ? different components contributing to dynamic power consumption in proasic3 devices parameter definition device specific dynamic power (w/mhz) a3p1000 a3p250 a3p125 a3p060 p ac1 clock contribution of a global rib 14.50 11.00 11.00 9.30 p ac2 clock contribution of a global spine 2.48 1.58 0.81 0.81 p ac3 clock contribution of a versatile row 0.81 p ac4 clock contribution of a versatile used as a sequential module 0.12 p ac5 first contribution of a versatil e used as a sequential module 0.07 p ac6 second contribution of a versatile used as a sequential module 0.29 p ac7 contribution of a versatile used as a combinatorial module 0.29 p ac8 average contribution of a routing net 0.70 p ac9 contribution of an i/o input pin (standard-dependent) see table 2-7 on page 2-6 . p ac10 contribution of an i/o output pin (standard-dependent) see ta b l e 2 - 7 and table 2-10 on page 2-8 . p ac11 average contribution of a ram bl ock during a read operation 25.00 p ac12 average contribution of a ram bl ock during a write operation 30.00 p ac13 static pll contribution 2.55 mw p ac14 dynamic contribution for pll 2.60 * for a different output load, drive st rength, or slew rate, actel recommends using the actel power spreadsheet calculator or smartpower tool in actel libero ? integrated design environment (ide).
automotive proasic3 dc and switching characteristics 2-10 revision 1 total static power consumption?p stat p stat = p dc1 + n inputs * p dc2 + n outputs * p dc3 n inputs is the number of i/o input buffers used in the design. n outputs is the number of i/o output buffers used in the design. total dynamic power consumption?p dyn p dyn = p clock + p s-cell + p c-cell + p net + p inputs + p outputs + p memory + p pll global clock contribution?p clock p clock = (p ac1 + n spine *p ac2 + n row * p ac3 + n s-cell * p ac4 ) * f clk n spine is the number of global spines used in the user design?guidelines are provided in table 2-12 on page 2-11 . n row is the number of versatile rows used in the design?guidelines are provided in table 2-12 on page 2-11 . f clk is the global clock signal frequency. n s-cell is the number of versatiles used as sequential modules in the design. p ac1 , p ac2 , p ac3 , and p ac4 are device-dependent. sequential cells contribution?p s-cell p s-cell = n s-cell * (p ac5 + 1 / 2 * p ac6 ) * f clk n s-cell is the number of versatiles used as sequent ial modules in the design. when a multi-tile sequential cell is used, it should be accounted for as 1. 1 is the toggle rate of versatile ou tputs?guidelines are provided in table 2-12 on page 2-11 . f clk is the global clock signal frequency. combinatorial cells contribution?p c-cell p c-cell = n c-cell * 1 / 2 * p ac7 * f clk n c-cell is the number of versatiles used as combinatorial modules in the design. 1 is the toggle rate of versatile ou tputs?guidelines are provided in table 2-12 on page 2-11 . f clk is the global clock signal frequency. routing net contribution?p net p net = (n s-cell + n c-cell ) * 1 / 2 * p ac8 * f clk n s-cell is the number versatiles used as sequential modules in the design. n c-cell is the number of versatiles used as combinatorial modules in the design. 1 is the toggle rate of versatile ou tputs?guidelines are provided in table 2-12 on page 2-11 . f clk is the global clock signal frequency. i/o input buffer contribution?p inputs p inputs = n inputs * 2 / 2 * p ac9 * f clk n inputs is the number of i/o input buffers used in the design. 2 is the i/o buffer toggle rate?guidelines are provided in table 2-12 on page 2-11 . f clk is the global clock signal frequency.
automotive proasic3 flash family fpgas revision 1 2-11 i/o output buffer contribution?p outputs p outputs = n outputs * 2 / 2 * 1 * p ac10 * f clk n outputs is the number of i/o output buffers used in the design. 2 is the i/o buffer toggle rate?guidelines are provided in ta b l e 2 - 1 2 . 1 is the i/o buffer enable rate?guidelines are provided in table 2-13 on page 2-12 . f clk is the global clock signal frequency. ram contribution?p memory p memory = p ac11 * n blocks * f read-clock * 2 + p ac12 * n block * f write-clock * 3 n blocks is the number of ram blocks used in the design. f read-clock is the memory read clock frequency. 2 is the ram enable rate for read operations. f write-clock is the memory write clock frequency. 3 is the ram enable rate for write operations?guidelines are provided in table 2-13 on page 2-12 . pll contribution?p pll p pll = p ac13 + p ac14 * f clkout f clkin is the input clock frequency. f clkout is the output clock frequency. 1 guidelines toggle rate definition a toggle rate defines the frequency of a net or logic elem ent relative to a clock. it is a percentage. if the toggle rate of a net is 100%, this means that this net switches at half the clock frequency. below are some examples: ? the average toggle rate of a shift register is 100% because all flip-flop outputs toggle at half of the clock frequency. ? the average toggle rate of an 8-bit counter is 25%: ? bit 0 (lsb) = 100% ? bit 1 = 50% ? bit 2 = 25% ?? ? bit 7 (msb) = 0.78125% ? average toggle rate = (100% + 50% + 25% + 12.5% + . . . + 0.78125%) / 8 enable rate definition output enable rate is the average percentage of ti me during which tristate outputs are enabled. when nontristate output buffers are used, the enable rate should be 100%. 1. the pll dynamic contribution depends on the input clock fr equency, the number of output clock signals generated by the pll, and the frequency of each output clock. if a pll is used to generate more than one output clock, include each output clock in the formula by adding its corresponding contribution (p ac14 * f clkout product) to the total pll contribution. table 2-12 ? toggle rate guidelines recommended for power calculation component definition guideline 1 toggle rate of versatile outputs 10% 2 i/o buffer toggle rate 10%
automotive proasic3 dc and switching characteristics 2-12 revision 1 user i/o characteristics timing model table 2-13 ? enable rate guidelines reco mmended for power calculation component definition guideline 1 i/o output buffer enable rate 100% 2 ram enable rate for read operations 12.5% 3 ram enable rate for write operations 12.5% figure 2-3 ? timing model operating conditions: ?1 speed, automotive grade 2 temp. range (t j = 115c), worst case vcc = 1.425 v dq y y dq dq dq y combinational cell combinational cell combinational cell i/o module (registered) i/o module (non-registered) register cell register cell i/o module (registered) i/o module (non-registered) lvpecl (applicable to advanced i/o banks only) lvpecl (applicable to advanced i/o banks only) lvds, blvds, m-lvds (applicable for advanced i/o banks only) lvttl 3.3 v output drive strength = 12 ma high slew rate y combinational cell y combinational cell y combinational cell i/o module (non-registered) lvttl output drive strength = 8 ma high slew rate i/o module (non-registered) lvcmos 1.5 v output drive strength = 4 ma high slew rate lvttl output drive strength = 12 ma high slew rate i/o module (non-registered) input lvttl clock input lvttl clock input lvttl clock t pd = 0.67 ns t pd = 0.58 ns t dp = 1.66 ns t pd = 1.04 ns t dp = 3.25 ns (advanced i/o banks) t pd = 0.60 ns t dp = 4.52 ns (advanced i/o banks) t pd = 0.56 ns t dp = 4.89 ns (advanced i/o banks) t pd = 0.56 ns t py = 0.94 ns (advanced i/o banks) t clkq = 0.66 ns t oclkq = 0.70 ns t sud = 0.51 ns t osud = 0.37 ns t dp = 3.25 ns (advanced i/o banks) t py = 0.94 ns (advanced i/o banks) t py = 1.47 ns t clkq = 0.66 ns t sud = 0.51 ns t py = 0.94 ns (advanced i/o banks) t iclkq = 0.29 ns t isud = 0.31 ns t py = 1.29 ns
automotive proasic3 flash family fpgas revision 1 2-13 figure 2-4 ? input buffer timing model and delays (example) t py (r) pad y v trip gnd t py (f) v trip 50% 50% vih vcc vil t dout (r) din gnd t dout (f) 50% 50% vcc pad y t py d clk q i/o interface din t din to array t py = max(t py (r), t py (f)) t din = max(t din (r), t din (f))
automotive proasic3 dc and switching characteristics 2-14 revision 1 figure 2-5 ? output buffer model and delays (example) t dp (r) pad v ol t dp (f) vtrip vtrip voh vcc d 50% 50% vcc 0 v dout 50% 50% 0 v t dout (r) t dout (f) from array pad t dp std load d clk q i/o interface dout d t dout t dp = max(t dp (r), t dp (f)) t dout = max(t dout (r), t dout (f))
automotive proasic3 flash family fpgas revision 1 2-15 figure 2-6 ? tristate output buffer timing model and delays (example) d clk q d clk q 10% v cci t zl vtrip 50% t hz 90% vcci t zh vtrip 50% 50% t lz 50% eout pad d e 50% t eout (r) 50% t eout (f) pad dout eout d i/o interface e t eout t zls vtrip 50% t zhs vtrip 50% eout pad d e 50% 50% t eout (r) t eout (f) 50% vcc vcc vcc vcci vcc vcc vcc voh vol vol t zl , t zh , t hz , t lz , t zls , t zhs t eout = max(t eout (r), t eout (f))
automotive proasic3 dc and switching characteristics 2-16 revision 1 overview of i/o performance summary of i/o dc input and output levels ? default i/o software settings table 2-14 ? summary of maximum and minimum dc input and output levels applicable to commercial and industrial conditions?s oftware default settings applicable to advanced i/o banks i/o standard drive strength slew rate vil vih vol voh i ol i oh min. v max. v min. v max. v max. v min. vmama 3.3 v lvttl / 3.3 v lvcmos 12 ma high ?0.3 0.8 2 3.6 0.4 2.4 12 12 2.5 v lvcmos 12 ma high ?0.3 0.7 1.7 3.6 0.7 1.7 12 12 1.8 v lvcmos 12 ma high ?0.3 0.35 * v cci 0.65 * vcci 3.6 0.45 vcci ? 0.45 12 12 1.5 v lvcmos 12 ma high ?0.3 0.30 * vcci 0. 7 * vcci 3.6 0.25 * vcci 0.75 * vcci 12 12 3.3 v pci per pci specifications 3.3 v pci-x per pci-x specifications note: currents are measured at 125c junction temperature. table 2-15 ? summary of maximum and minimum dc input and output levels applicable to commercial and industrial conditions?s oftware default settings applicable to standard plus i/o banks i/o standard drive strength slew rate vil vih vol voh i ol i oh min. v max. v min. v max. v max. v min. vmama 3.3 v lvttl / 3.3 v lvcmos 12 ma high ?0.3 0.8 2 3.6 0.4 2.4 12 12 2.5 v lvcmos 12 ma high ?0.3 0.7 1.7 3.6 0.7 1.7 12 12 1.8 v lvcmos 8 ma high ?0.3 0.35 * vcci 0.65 * vcci 3.6 0.45 vcci ? 0.45 8 8 1.5 v lvcmos 4 ma high ?0.3 0.30 * vcci 0.7 * v cci 3.6 0.25 * vcci 0.75 * v cci 4 4 3.3 v pci per pci specifications 3.3 v pci-x per pci-x specifications note: currents are measured at 125c junction temperature.
automotive proasic3 flash family fpgas revision 1 2-17 summary of i/o timing char acteristics ? default i/o software settings table 2-16 ? summary of maximum and minimum dc input and output levels applicable to commercial and industrial conditions?s oftware default settings applicable to standard i/o banks i/o standard drive strength slew rate vil vih vol voh i ol i oh min. v max. v min. v max. v max. v min. vmama 3.3 v lvttl / 3.3 v lvcmos 8 ma high ?0.3 0.8 2 3.6 0.4 2.4 8 8 2.5 v lvcmos 8 ma high ?0.3 0.7 1.7 3.6 0.7 1.7 8 8 1.8 v lvcmos 4 ma high ?0.3 0.35 * v cci 0.65 * vcci 3.6 0.45 vcci ? 0.45 4 4 1.5 v lvcmos 2 ma high ?0.3 0.30 * vcci 0.7 * vcci 3.6 0.25 * vcci 0.75 * vcci 2 2 note: currents are measured at 125c junction temperature. table 2-17 ? summary of maximum and minimum dc input levels applicable to automotive grade 1 and grade 2 dc i/o standards automotive grade 1 1 automotive grade 2 2 i il i ih i il i ih a a a a 3.3 v lvttl / 3.3 v lvcmos 10 10 15 15 2.5 v lvcmos 10 10 15 15 1.8 v lvcmos 10 10 15 15 1.5 v lvcmos 10 10 15 15 3.3 v pci 10 10 15 15 3.3 v pci-x 10 10 15 15 notes: 1. automotive range grade 1 (?40c < t j < 135c) 2. automotive range grade 2 (?40c < t j < 115c) table 2-18 ? summary of ac measuring points standard measuring trip point (v trip ) 3.3 v lvttl / 3.3 v lvcmos 1.4 v 2.5 v lvcmos 1.2 v 1.8 v lvcmos 0.90 v 1.5 v lvcmos 0.75 v 3.3 v pci 0.285 * vcci (rr) 0.615 * vcci (ff) 3.3 v pci-x 0.285 * vcci (rr) 0.615 * vcci (ff)
automotive proasic3 dc and switching characteristics 2-18 revision 1 table 2-19 ? i/o ac parameter definitions parameter parameter definition t dp data-to-pad delay through the output buffer t py pad-to-data delay through the input buffer t dout data?to?output buffer delay through the i/o interface t eout enable?to?output buffer tristate c ontrol delay through the i/o interface t din input buffer?to?data delay through the i/o interface t hz enable-to-pad delay through the output buffer?high to z t zh enable-to-pad delay through the output buffer?z to high t lz enable-to-pad delay through the output buffer?low to z t zl enable-to-pad delay through the output buffer?z to low t zhs enable-to-pad delay through the output buffer with delayed enable?z to high t zls enable-to-pad delay through the output buffer with delayed enable?z to low table 2-20 ? summary of i/o timing character istics?software default settings ?1 speed grade, automotive-case conditions: t j = 115c, worst case vcc = 1.425 v worst case vcci = 3.0 v advanced i/o banks i/o standard drive strength (ma) slew rate capacitive load (pf) external resistor ( ) t dout (ns) t dp (ns) t din (ns) t py (ns) t eout (ns) t zl (ns) t zh (ns) t lz (ns) t hz (ns) t zls (ns) t zhs (ns) units 3.3 v lvttl / 3.3 v lvcmos 12 ma high35 pf ? 0.533.250.040.940.383.311.512.961.885.372.71ns 2.5 v lvcmos 12 ma high35 pf ? 0.533.280.041.190.383.343.161.771.805.395.22ns 1.8 v lvcmos 12 ma high35 pf ? 0.533.250.041.120.381.891.633.413.753.062.82ns 1.5 v lvcmos 12 ma high35 pf ? 0.533.750.041.320.382.181.913.633.873.353.11ns 3.3 v pci per pci spec high 10 pf 25 2 0.53 2.12 0.04 0.78 0.38 1.23 0.91 2.57 2.96 2.41 2.11 ns 3.3 v pci-x per pci-x spec high 10 pf 25 2 0.53 2.47 0.04 0.77 0.38 1.23 0.91 2.57 2.96 2.41 2.11 ns lvds 24 ma high ? ? 0.53 1.68 0.04 1.47 ? ? ? ? ? ? ? ns lvpecl 24 ma high ? ? 0.53 1.66 0.04 1.29 ? ? ? ? ? ? ? ns notes: 1. for specific junction temperature and voltage supply levels, refer to table 2-5 on page 2-5 for derating values. 2. resistance is used to measure i/o propagation delays as defined in pci specifications. see figure 2-11 on page 2-48 for connectivity. this resistor is not required during normal operation.
automotive proasic3 flash family fpgas revision 1 2-19 table 2-21 ? summary of i/o timing character istics?software default settings ?1 speed grade, automotive-case conditions: t j = 115c, worst case vcc = 1.425 v worst case vcci = 3.0 v standard plus i/o banks i/o standard drive strength (ma) slew rate capacitive load (pf) external resistor t dout t dp t din t py t eout t zl t zh t lz t hz t zls t zhs units 3.3 v lvttl / 3.3 v lvcmos 12 ma high 35 pf ? 0.55 3.01 0.04 0.95 0.39 1.74 1.43 2.65 3.06 1.74 1.43 ns 2.5 v lvcmos 12 ma high 35 pf ? 0.55 3.05 0. 04 1.23 0.39 3.11 2.99 1.56 1.69 5.23 5.11 ns 1.8 v lvcmos 8 ma high 35 pf ? 0.55 3.73 0. 04 1.16 0.39 3.65 3.86 1.62 1.68 5.78 5.99 ns 1.5 v lvcmos 4 ma high 35 pf ? 0.55 4.60 0. 04 1.35 0.39 4.61 5.05 2.07 1.85 6.74 7.18 ns 3.3 v pci per pci spec high 10 pf 25 2 0.55 2.19 0.04 0.81 0.39 1.27 0.94 2.65 3.06 1.27 0.94 ns 3.3 v pci-x per pci-x spec high 10 pf 25 2 0.55 2.19 0.04 0.79 0.39 1.27 0.94 2.65 3.06 1.27 0.94 ns notes: 1. for specific junction temperature and voltage supply levels, refer to table 2-5 on page 2-5 for derating values. 2. resistance is used to measure i/o propagation delays as defined in pci specifications. see figure 2-11 on page 2-48 for connectivity. this resistor is not required during normal operation.
automotive proasic3 dc and switching characteristics 2-20 revision 1 table 2-22 ? summary of i/o timing character istics?software default settings ?1 speed grade, automotive-case conditions: t j = 135c, worst case vcc = 1.425 v worst case vcci = 3.0 v advanced i/o banks i/o standard drive strength (ma) slew rate capacitive load (pf) external resistor ( ) t dout (ns) t dp (ns) t din (ns) t py (ns) t eout (ns) t zl (ns) t zh (ns) t lz (ns) t hz (ns) t zls (ns) t zhs (ns) units 3.3 v lvttl / 3.3 v lvcmos 12 ma high 35 pf ? 0.55 3.36 0.04 0.97 0.39 3.42 1.56 3.05 1.94 5.55 2.80 ns 2.5 v lvcmos 12 ma high 35 pf ? 0.55 3.39 0. 04 1.23 0.39 3.45 3.27 1.83 1.86 5.58 5.39 ns 1.8 v lvcmos 12 ma high 35 pf ? 0.55 3.36 0. 04 1.16 0.39 1.95 1.68 3.52 3.88 3.16 2.92 ns 1.5 v lvcmos 12 ma high 35 pf ? 0.55 3.88 0. 04 1.37 0.39 2.25 1.98 3.75 4.00 3.46 3.21 ns 3.3 v pci per pci spec high 10 pf 25 2 0.55 2.19 0.04 0.81 0.39 1.27 0.94 2.65 3.06 2.49 2.18 ns 3.3 v pci-x per pci-x spec high 10 pf 25 2 0.55 2.55 0.04 0.79 0.39 1.27 0.94 2.65 3.06 2.49 2.18 ns lvds 24 ma high ? ? 0.55 1.74 0.04 1.52 ? ? ? ? ? ? ? ns lvpecl 24 ma high ? ? 0.55 1.71 0.04 1.34 ? ? ? ? ? ? ? ns notes: 1. for specific junction temperature and voltage supply levels, refer to table 2-5 on page 2-5 for derating values. 2. resistance is used to measure i/o propagation delays as defined in pci specifications. see figure 2-11 on page 2-48 for connectivity. this resistor is not required during normal operation.
automotive proasic3 flash family fpgas revision 1 2-21 table 2-23 ? summary of i/o timing character istics?software default settings ?1 speed grade, automotive-case conditions: t j = 115c, worst case vcc = 1.425 v worst case vcci = 3.0 v standard plus i/o banks i/o standard drive strength (ma) slew rate capacitive load (pf) external resistor t dout (ns) t dp (ns) t din (ns) t py (ns) t eout (ns) t zl (ns) t zh (ns) t lz (ns) t hz (ns) t zls (ns) t zhs (ns) units 3.3 v lvttl / 3.3 v lvcmos 12 ma high 35 pf ? 0.55 3.36 0.04 0.97 0.39 3.42 1.56 3.05 1.94 5.55 2.80 ns 2.5 v lvcmos 12 ma high 35 pf ? 0.55 3.05 0. 04 1.23 0.39 3.11 2.99 1.56 1.69 5.23 5.11 ns 1.8 v lvcmos 8 ma high 35 pf ? 0.55 3.73 0. 04 1.16 0.39 3.65 3.86 1.62 1.68 5.78 5.99 ns 1.5 v lvcmos 4 ma high 35 pf ? 0.55 4.60 0. 04 1.35 0.39 4.61 5.05 2.07 1.85 6.74 7.18 ns 3.3 v pci per pci spec high 10 pf 25 2 0.55 2.55 0.04 0.82 0.39 1.27 0.94 2.65 3.06 2.49 2.18 ns 3.3 v pci-x per pci-x spec high 10 pf 25 2 0.55 2.55 0.04 0.79 0.39 1.27 0.94 2.65 3.06 2.49 2.18 ns notes: 1. for specific junction temperature and voltage supply levels, refer to table 2-5 on page 2-5 for derating values. 2. resistance is used to measure i/o propagation delays as defined in pci specifications. see figure 2-11 on page 2-48 for connectivity. this resistor is not required during normal operation.
automotive proasic3 dc and switching characteristics 2-22 revision 1 detailed i/o dc characteristics table 2-24 ? input capacitance symbol definition cond itions min. max. units c in input capacitance v in = 0, f = 1.0 mhz 8 pf c inclk input capacitance on the clock pin v in = 0, f = 1.0 mhz 8 pf table 2-25 ? i/o output buffer maximum resistances 1 applicable to advanced i/o banks standard drive strength r pull-down ( ) 2 r pull-up ( ) 3 3.3 v lvttl / 3.3 v lvcmos 2 ma 100 300 4 ma 100 300 6 ma 50 150 8 ma 50 150 12 ma 25 75 16 ma 17 50 24 ma 11 33 2.5 v lvcmos 2 ma 100 200 6 ma 50 100 12 ma 25 50 16 ma 20 40 24 ma 11 22 1.8 v lvcmos 2 ma 200 225 4 ma 100 112 6 ma 50 56 8 ma 50 56 12 ma 20 22 16 ma 20 22 1.5 v lvcmos 2 ma 200 224 4 ma 100 112 6 ma 67 75 8 ma 33 37 12 ma 33 37 3.3 v pci/pci-x per pci/pci-x specification 25 75 notes: 1. these maximum values are provided for informational reasons only. minimum output buffer resistance values depend on v cci , drive strength selection, temperature, and process. for board design considerations and detailed output buffer resistances, use the corresponding ibis models located on the actel website at http://www.actel.com/download/ibis/default.aspx . 2. r (pull-down-max) = (volspec) / i olspec 3. r (pull-up-max) = (vccimax ? vohspec) / i ohspec
automotive proasic3 flash family fpgas revision 1 2-23 table 2-26 ? i/o output buffer maximum resistances 1 applicable to standard plus i/o banks standard drive strength r pull-down ( ) 2 r pull-up ( ) 3 3.3 v lvttl / 3.3 v lvcmos 2 ma 100 300 4 ma 100 300 6 ma 50 150 8 ma 50 150 12 ma 25 75 16 ma 25 75 2.5 v lvcmos 2 ma 100 200 6 ma 50 100 12 ma 25 50 1.8 v lvcmos 2 ma 200 225 4 ma 100 112 6 ma 50 56 8 ma 50 56 1.5 v lvcmos 2 ma 200 224 4 ma 100 112 3.3 v pci/pci-x per pci/pci-x specification 0 0 notes: 1. these maximum values are provided for informational reasons only. minimum output buffer resistance values depend on v cci , drive strength selection, temperature, and process. for board design considerations and detailed output buffer resistances, use the corresponding ibis models located on the actel website at http://www.actel.com/download/ibis/default.aspx . 2. r (pull-down-max) = (volspec) / i olspec 3. r (pull-up-max) = (vccimax ? vohspec) / i ohspec table 2-27 ? i/o weak pull-up/pull-down resistances minimum and maximum weak pull-u p/pull-down resistance values v cci r (weak pull-up) 1 ( ) r (weak pull-down) 2 ( ) min. max. min. max. 3.3 v 10 k 45 k 10 k 45 k 2.5 v 11 k 55 k 12 k 74 k 1.8 v 18 k 70 k 17 k 110 k 1.5 v 19 k 90 k 19 k 140 k notes: 1. r (weak pull-up-max) = (v olspec ) / i (weak pull-up-min) 2. r (weak pull-up-max) = (v ccimax ? v ohspec ) / i (weak pull-up-min)
automotive proasic3 dc and switching characteristics 2-24 revision 1 table 2-28 ? i/o short currents i osh /i osl applicable to advanced i/o banks drive strength i osl (ma)* i osh (ma)* 3.3 v lvttl / 3.3 v lvcmos 2 ma 27 25 4 ma 27 25 6 ma 54 51 8 ma 54 51 12 ma 109 103 16 ma 127 132 24 ma 181 268 3.3 v lvcmos 2 ma 27 25 4 ma 27 25 6 ma 54 51 8 ma 54 51 12 ma 109 103 16 ma 127 132 24 ma 181 268 2.5 v lvcmos 2 ma 18 16 6 ma 37 32 12 ma 74 65 16 ma 87 83 24 ma 124 169 1.8 v lvcmos 2 ma 11 9 4 ma 22 17 6 ma 44 35 8 ma 51 45 12 ma 74 91 16 ma 74 91 1.5 v lvcmos 2 ma 16 13 4 ma 33 25 6 ma 39 32 8 ma 55 66 12 ma 55 66 3.3 v pci/pci-x per pci/pci-x specification 109 103 * t j = 100c
automotive proasic3 flash family fpgas revision 1 2-25 the length of time an i/o can withstand i osh /i osl events depends on the junction temperature. the reliability data below is based on a 3.3 v, 12 ma i/o setting, which is the worst case for this type of analysis. for example, at 110c, the short current conditi on would have to be sustained for more than three months to cause a reliability conc ern. the i/o design does not contai n any short circuit protection, but such protection would only be needed in extremely prolonged stress conditions. table 2-29 ? i/o short currents i osh /i osl applicable to standard plus i/o banks drive strength i osl (ma)* i osh (ma)* 3.3 v lvttl / 3.3 v lvcmos 2 ma 27 25 4 ma 27 25 6 ma 54 51 8 ma 54 51 12 ma 109 103 16 ma 109 103 2.5 v lvcmos 2 ma 18 16 6 ma 37 32 12 ma 74 65 1.8 v lvcmos 2 ma 11 9 4 ma 22 17 6 ma 44 35 8 ma 44 35 1.5 v lvcmos 2 ma 16 13 4 ma 33 25 3.3 v pci/pci-x per pci/pci-x specification 109 103 * t j = 100c table 2-30 ? duration of short circui t event before failure temperature time before failure ?40c > 20 years 0c > 20 years 25c > 20 years 70c 5 years 85c 2 years 100c 6 months 110c 3 months 125c 25 days 135 12 days
automotive proasic3 dc and switching characteristics 2-26 revision 1 table 2-31 ? i/o input rise time, fall time , and related i/o reliability input buffer input rise/fall time (min.) input rise/fall time (max.) reliability lvttl/lvcmos no requirement 10 ns * 20 years (110c) lvds/b-lvds/m- lvds/lvpecl no requirement 10 ns * 10 years (100c) * the maximum input rise/fall time is related to the noise induced into the input buffer trace. if the noise is low, the rise time and fall time of input buffers can be increased beyond the maximum value. the longer the rise/fall times, the more susceptible the input signal is to the board noise. actel recommends signal integrity evaluation/characterization of the system to ensure there is no excessive noise coupling into input signals.
automotive proasic3 flash family fpgas revision 1 2-27 single-ended i/o characteristics 3.3 v lvttl / 3.3 v lvcmos low-voltage transistor?transistor logic (lvttl) is a general-purpose standard (eia/jesd) for 3.3 v applications. it uses an lvttl input buffer and push-pull output buffer. table 2-32 ? minimum and maximum dc input and output levels applicable to advanced i/o banks 3.3 v lvttl / 3.3 v lvcmos vil vih vol voh i ol i oh i osl i osh i il i ih drive strength min. v max. v min. v max. v max. v min. vmama max. ma 1 max. ma 1 a 2 a 2 2 ma ?0.3 0.8 2 3.6 0.4 2.4 2 2 27 25 10 10 4 ma ?0.3 0.8 2 3.6 0.4 2.4 4 4 27 25 10 10 6 ma ?0.3 0.8 2 3.6 0.4 2.4 6 6 54 51 10 10 8 ma ?0.3 0.8 2 3.6 0.4 2.4 8 8 54 51 10 10 12 ma ?0.3 0.8 2 3.6 0.4 2.4 12 12 109 103 10 10 16 ma ?0.3 0.8 2 3.6 0.4 2.4 16 16 127 132 10 10 24 ma ?0.3 0.8 2 3.6 0.4 2.4 24 24 181 268 10 10 notes: 1. currents are measured at high temperature (100 c junction temperature) and maximum voltage. 2. currents are measured at 125c junction temperature. 3. software default selection highlighted in gray. table 2-33 ? minimum and maximum dc input and output levels applicable to standard plus i/o banks 3.3 v lvttl / 3.3 v lvcmos vil vih vol voh i ol i oh i osl i osh i il i ih drive strength min. v max. v min. v max. v max. v min. vmama max. ma 1 max. ma 1 a 2 a 2 2 ma ?0.3 0.8 2 3.6 0.4 2.4 2 2 27 25 10 10 4 ma ?0.3 0.8 2 3.6 0.4 2.4 4 4 27 25 10 10 6 ma ?0.3 0.8 2 3.6 0.4 2.4 6 6 54 51 10 10 8 ma ?0.3 0.8 2 3.6 0.4 2.4 8 8 54 51 10 10 12 ma ?0.3 0.8 2 3.6 0.4 2.4 12 12 109 103 10 10 16 ma ?0.3 0.8 2 3.6 0.4 2.4 16 16 109 103 10 10 notes: 1. currents are measured at high temperature (100 c junction temperature) and maximum voltage. 2. currents are measured at 125c junction temperature. 3. software default selection highlighted in gray.
automotive proasic3 dc and switching characteristics 2-28 revision 1 figure 2-7 ? ac loading table 2-34 ? ac waveforms, measuring points, and capacitive loads input low (v) input high (v) measuring point* (v) c load (pf) 03.31.435 * measuring point = v trip. see table 2-18 on page 2-17 for a complete table of trip points. test point test point enable path datapath 35 pf r = 1 k r to vcci for t lz / t zl / t zls r to gnd for t hz / t zh / t zhs 35 pf for t zh / t zhs / t zl / t zls 5 pf for t hz / t lz
automotive proasic3 flash family fpgas revision 1 2-29 timing characteristics table 2-35 ? 3.3 v lvttl / 3.3 v lvcmos high slew automotive-case conditions: t j = 135c, worst-case vcc = 1.425 v, worst-case vcci = 3.0 v applicable to advanced i/o banks drive strength speed grade t dout t dp t din t py t eout t zl t zh t lz t hz t zls t zhs units 4 ma std 0.64 8.56 0.05 1.14 0.46 8 .72 7.37 1.46 1.42 11.22 9.866 ns -1 0.55 7.28 0.04 0.97 0.39 7.42 6.27 1.46 1.42 9.54 8.393 ns 6 ma std 0.64 5.49 0.05 1.14 0.46 5 .59 4.55 1.65 1.74 8.09 7.05 ns -1 0.55 4.67 0.04 0.97 0.39 4.75 3.87 1.65 1.74 6.88 5.997 ns 8 ma std 0.64 5.49 0.05 1.14 0.46 5 .59 4.55 1.65 1.74 8.09 7.05 ns -1 0.55 4.67 0.04 0.97 0.39 4.75 3.87 1.65 1.74 6.88 5.997 ns 12 ma std 0.64 3.95 0.05 1.14 0.46 4.02 1.56 3.59 1.94 6.52 2.795 ns -1 0.55 3.36 0.04 0.97 0.39 3.42 1.56 3.05 1.94 5.55 2.797 ns 16 ma std 0.64 3.73 0.05 1.14 0.46 1.84 1.42 3.65 4.11 3.05 2.651 ns -1 0.55 3.17 0.04 0.97 0.39 1.84 1.42 3.10 3.50 3.05 2.653 ns 24 ma std 0.64 3.44 0.05 1.14 0.46 1.70 1.17 3.72 4.54 2.91 2.405 ns -1 0.55 2.92 0.04 0.97 0.39 1.70 1.17 3.16 3.86 2.91 2.407 ns notes: 1. software default selection highlighted in gray. 2. for specific junction temperature and voltage supply levels, refer to table 2-5 on page 2-5 for derating values. table 2-36 ? 3.3 v lvttl / 3.3 v lvcmos low slew automotive-case conditions: t j = 135c, worst-case vcc = 1.425 v, worst-case vcci = 3.0 v applicable to advanced i/o banks drive strength speed grade t dout t dp t din t py t eout t zl t zh t lz t hz t zls t zhs units 4 ma std 0.64 11.47 0.05 1.14 0.46 11.68 9.95 1.46 1.33 14.18 12.449 ns -1 0.55 9.75 0.04 0.97 0.39 9.94 8.46 1.46 1.33 12.06 10.59 ns 6 ma std 0.64 8.13 0.05 1.14 0.46 8.28 7.03 1.65 1.65 10.79 9.526 ns -1 0.55 6.92 0.04 0.97 0.39 7. 05 5.98 1.65 1.65 9.17 8.103 ns 8 ma std 0.64 8.13 0.05 1.14 0.46 8.28 7.03 1.65 1.65 10.79 9.526 ns -1 0.55 6.92 0.04 0.97 0.39 7. 05 5.98 1.65 1.65 9.17 8.103 ns 12 ma std 0.64 6.24 0.05 1.14 0.46 6.36 5.45 1.77 1.85 8.86 7.946 ns -1 0.55 5.31 0.04 0.97 0.39 5. 41 4.63 1.77 1.85 7.53 6.76 ns 16 ma std 0.64 5.82 0.05 1.14 0.46 5.93 5.10 1.80 1.90 8.43 7.604 ns -1 0.55 4.95 0.04 0.97 0.39 5. 04 4.34 1.80 1.90 7.17 6.468 ns 24 ma std 0.64 5.42 0.05 1.14 0.46 5.52 5.08 1.83 2.10 8.02 7.581 ns -1 0.55 4.61 0.04 0.97 0.39 4. 70 4.32 1.83 2.11 6.82 6.449 ns note: for specific junction temperature and voltage supply levels, refer to table 2-5 on page 2-5 for derating values.
automotive proasic3 dc and switching characteristics 2-30 revision 1 table 2-37 ? 3.3 v lvttl / 3.3 v lvcmos high slew automotive-case conditions: t j = 135c, worst-case vcc = 1.425 v, worst-case vcci = 3.0 v applicable to standard plus i/o banks drive strength speed grade t dout t dp t din t py t eout t zl t zh t lz t hz t zls t zhs units 4 ma std 0.64 8.06 0.05 1.12 0.46 8.20 7.03 1.26 1.27 8.20 7.027 ns -1 0.55 6.85 0.04 .095 0.39 6.98 5.98 1.26 1.27 6.98 5.978 ns 6 ma std 0.64 5.03 0.05 1.12 0.46 5.13 4.27 1.42 1.56 5.13 4.267 ns -1 0.55 4.28 0.04 0.95 0.39 4. 36 3.63 1.42 1.56 4.36 3.63 ns 8 ma std 0.64 5.03 0.05 1.12 0.46 5.13 4.27 1.42 1.56 5.13 4.267 ns -1 0.55 4.28 0.04 0.95 0.39 4. 36 3.63 1.42 1.56 4.36 3.63 ns 12 ma std 0.64 3.53 0.05 1.12 0.46 1.74 1.43 3.12 3.60 1.74 1.427 ns -1 0.55 3.01 0.04 0.95 0.39 1.74 1.43 2.65 3.06 1.74 1.428 ns 16 ma std 0.64 3.53 0.05 1.12 0.46 1.74 1.43 3.12 3.60 1.74 1.427 ns -1 0.55 3.01 0.04 0.95 0.39 1.74 1.43 2.65 3.06 1.74 1.428 ns notes: 1. software default selection highlighted in gray. 2. for specific junction temperature and voltage supply levels, refer to table 2-5 on page 2-5 for derating values. table 2-38 ? 3.3 v lvttl / 3.3 v lvcmos low slew automotive-case conditions: t j = 135c, worst-case vcc = 1.425 v, worst-case vcci = 3.0 v applicable to standard plus i/o banks drive strength speed grade t dout t dp t din t py t eout t zl t zh t lz t hz t zls t zhs units 4 ma std 0.64 10.82 0.05 1.12 0.46 11.02 9.42 1.26 1.20 11.02 9.419 ns -1 0.55 9.21 0.04 0.95 0.39 9. 38 8.01 1.26 1.20 9.38 8.012 ns 6 ma std 0.64 7.49 0.05 1.12 0.46 7.63 6.58 1.43 1.48 7.63 6.58 ns -1 0.55 6.37 0.04 0.95 0.39 6. 49 5.60 1.43 1.49 6.49 5.598 ns 8 ma std 0.64 7.49 0.05 1.12 0.46 7.63 6.58 1.43 1.48 7.63 6.58 ns -1 0.55 6.37 0.04 0.95 0.39 6. 49 5.60 1.43 1.49 6.49 5.598 ns 12 ma std 0.64 5.64 0.05 1.12 0.46 5.75 5.04 1.54 1.67 5.75 5.042 ns -1 0.55 4.80 0.04 0.95 0.39 4. 89 4.29 1.54 1.67 4.89 4.289 ns 16 ma std 0.64 5.64 0.05 1.12 0.46 5.75 5.04 1.54 1.67 5.75 5.042 ns -1 0.55 4.80 0.04 0.95 0.39 4. 89 4.29 1.54 1.67 4.89 4.289 ns note: for specific junction temperature and voltage supply levels, refer to table 2-5 on page 2-5 for derating values.
automotive proasic3 flash family fpgas revision 1 2-31 table 2-39 ? 3.3 v lvttl / 3.3 v lvcmos high slew automotive-case conditions: t j = 115c, worst-case vcc = 1.425 v, worst-case vcci = 3.0 v applicable to advanced i/o banks drive strength speed grade t dout t dp t din t py t eout t zl t zh t lz t hz t zls t zhs units 4 ma std 0.63 8.28 0.05 1.10 0.45 8.44 7.13 1.42 1.37 10.85 9.55 ns -1 0.53 7.05 0.04 0.94 0.38 7. 18 6.06 1.42 1.37 9.23 8.12 ns 6 ma std 0.63 5.31 0.05 1.10 0.45 5.41 4.40 1.60 1.68 7.83 6.82 ns -1 0.53 4.52 0.04 0.94 0.38 4. 60 3.74 1.60 1.68 6.66 5.80 ns 8 ma std 0.63 5.31 0.05 1.10 0.45 5.41 4.40 1.60 1.68 7.83 6.82 ns -1 0.53 4.52 0.04 0.94 0.38 4. 60 3.74 1.60 1.68 6.66 5.80 ns 12 ma std 0.63 3.82 0.05 1.10 0.45 3.89 1.51 3.47 1.88 6.31 2.70 ns -1 0.53 3.25 0.04 0.94 0.38 3.31 1.51 2.96 1.88 5.37 2.71 ns 16 ma std 0.63 3.60 0.05 1.10 0.45 1.78 1.37 3.53 3.98 2.95 2.57 ns -1 0.53 3.07 0.04 0.94 0.38 1. 78 1.37 3.00 3.38 2.95 2.57 ns 24 ma std 0.63 3.33 0.05 1.10 0.45 1.64 1.13 3.60 4.39 2.81 2.33 ns -1 0.53 2.83 0.04 0.94 0.38 1. 64 1.13 3.06 3.74 2.82 2.33 ns notes: 1. software default selection highlighted in gray. 2. for specific junction temperature and voltage supply levels, refer to table 2-5 on page 2-5 for derating values. table 2-40 ? 3.3 v lvttl / 3.3 v lvcmos low slew automotive-case conditions: t j = 115c, worst-case vcc = 1.425 v, worst-case vcci = 3.0 v applicable to advanced i/o banks drive strength speed grade t dout t dp t din t py t eout t zl t zh t lz t hz t zls t zhs units 4 ma std 0.63 11.09 0.05 1.10 0.45 11.30 9.63 1.41 1.29 13.72 12.04 ns -1 0.53 9.44 0.04 0.94 0.38 9.61 8.19 1.41 1.29 11.67 10.25 ns 6 ma std 0.63 7.87 0.05 1.10 0.45 8.02 6.80 1.59 1.59 10.43 9.22 ns -1 0.53 6.69 0.04 0.94 0.38 6. 82 5.78 1.59 1.60 8.88 7.84 ns 8 ma std 0.63 7.87 0.05 1.10 0.45 8.02 6.80 1.59 1.59 10.43 9.22 ns -1 0.53 6.69 0.04 0.94 0.38 6. 82 5.78 1.59 1.60 8.88 7.84 ns 12 ma std 0.63 6.04 0.05 1.10 0.45 6.15 5.27 1.71 1.79 8.57 7.69 ns -1 0.53 5.14 0.04 0.94 0.38 5. 23 4.48 1.71 1.79 7.29 6.54 ns 16 ma std 0.63 5.63 0.05 1.10 0.45 5.74 4.94 1.74 1.84 8.16 7.36 ns -1 0.53 4.79 0.04 0.94 0.38 4. 88 4.20 1.74 1.84 6.94 6.26 ns 24 ma std 0.63 5.25 0.05 1.10 0.45 5.34 4.92 1.77 2.04 7.76 7.34 ns -1 0.53 4.46 0.04 0.94 0.38 4. 55 4.18 1.77 2.04 6.60 6.24 ns note: for specific junction temperature and voltage supply levels, refer to table 2-5 on page 2-5 for derating values.
automotive proasic3 dc and switching characteristics 2-32 revision 1 table 2-41 ? 3.3 v lvttl / 3.3 v lvcmos high slew automotive-case conditions: t j = 115c, worst-case vcc = 1.425 v, worst-case vcci = 3.0 v applicable to standard plus i/o banks drive strength speed grade t dout t dp t din t py t eout t zl t zh t lz t hz t zls t zhs units 4 ma std 0.63 7.79 0.05 1.08 0.45 7.94 6.80 1.22 1.23 7.94 6.80 ns -1 0.55 6.85 0.04 0.95 0.39 6. 98 5.98 1.26 1.27 6.98 5.98 ns 6 ma std 0.63 4.87 0.05 1.08 0.45 4.96 4.13 1.38 1.51 4.96 4.13 ns -1 0.55 4.28 0.04 0.95 0.39 4. 36 3.63 1.42 1.56 4.36 3.63 ns 8 ma std 0.63 4.87 0.05 1.08 0.45 4.96 4.13 1.38 1.51 4.96 4.13 ns -1 0.55 4.28 0.04 0.95 0.39 4. 36 3.63 1.42 1.56 4.36 3.63 ns 12 ma std 0.63 3.42 0.05 1.08 0.45 1.69 1.38 3.02 3.48 1.69 1.38 ns -1 0.55 3.01 0.04 0.95 0.39 1.74 1.43 2.65 3.06 1.74 1.43 ns 16 ma std 0.63 3.42 0.05 1.08 0.45 1.69 1.38 3.02 3.48 1.69 1.38 ns -1 0.55 3.01 0.04 0.95 0.39 1. 74 1.43 2.65 3.06 1.74 1.43 ns notes: 1. software default selection highlighted in gray. 2. for specific junction temperature and voltage supply levels, refer to table 2-5 on page 2-5 for derating values. table 2-42 ? 3.3 v lvttl / 3.3 v lvcmos low slew automotive-case conditions: t j = 115c, worst-case vcc = 1.425 v, worst-case vcci = 3.0 v applicable to standard plus i/o banks drive strength speed grade t dout t dp t din t py t eout t zl t zh t lz t hz t zls t zhs units 4 ma std 0.63 10.47 0.05 1.08 0.45 10.66 9.11 1.22 1.16 10.66 9.11 ns -1 0.55 9.21 0.04 0.95 0.39 9. 38 8.01 1.26 1.20 9.38 8.01 ns 6 ma std 0.63 7.25 0.05 1.08 0.45 7.38 6.37 1.38 1.44 7.38 6.37 ns -1 0.55 6.37 0.04 0.95 0.39 6. 49 5.60 1.43 1.49 6.49 5.60 ns 8 ma std 0.63 7.25 0.05 1.08 0.45 7.38 6.37 1.38 1.44 7.38 6.37 ns -1 0.55 6.37 0.04 0.95 0.39 6. 49 5.60 1.43 1.49 6.49 5.60 ns 12 ma std 0.63 5.46 0.05 1.08 0.45 5.56 4.88 1.49 1.61 5.56 4.88 ns -1 0.55 4.80 0.04 0.95 0.39 4. 89 4.29 1.54 1.67 4.89 4.29 ns 16 ma std 0.63 5.46 0.05 1.08 0.45 5.56 4.88 1.49 1.61 5.56 4.88 ns -1 0.55 4.80 0.04 0.95 0.39 4. 89 4.29 1.54 1.67 4.89 4.29 ns note: for specific junction temperature and voltage supply levels, refer to table 2-5 on page 2-5 for derating values.
automotive proasic3 flash family fpgas revision 1 2-33 2.5 v lvcmos low-voltage cmos for 2.5 v is an extension of the lvcmos standard (jesd8-5) used for general- purpose 2.5 v applications. it uses a 5 v?toler ant input buffer and push-pull output buffer. table 2-43 ? minimum and maximum dc input and output levels applicable to advanced i/o banks 2.5 v lvcmos vil vih v ol voh i ol i oh i osl i osh i il i ih drive strength min. v max. v min. v max. v max. v min. vmama max. ma 1 max. ma 1 a 2 a 2 2 ma ?0.3 0.7 1.7 3.6 0.7 1.7 2 2 18 16 10 10 6 ma ?0.3 0.7 1.7 3.6 0.7 1.7 6 6 37 32 10 10 12 ma ?0.3 0.7 1.7 3.6 0.7 1.7 12 12 74 65 10 10 16 ma ?0.3 0.7 1.7 3.6 0.7 1.7 16 16 87 83 10 10 24 ma ?0.3 0.7 1.7 3.6 0.7 1.7 24 24 124 169 10 10 notes: 1. currents are measured at high temperature (100 c junction temperature) and maximum voltage. 2. currents are measured at 125c junction temperature. 3. software default selection highlighted in gray. table 2-44 ? minimum and maximum dc input and output levels applicable to standard plus i/o banks 2.5 v lvcmos vil vih v ol voh i ol i oh i osl i osh i il i ih drive strength min. v max. v min. v max. v max. v min. vmamamax., ma 1 max., ma 1 a 2 a 2 2 ma ?0.3 0.7 1.7 3.6 0.7 1.7 2 2 18 16 10 10 6 ma ?0.3 0.7 1.7 3.6 0.7 1.7 6 6 37 32 10 10 12 ma ?0.3 0.7 1.7 3.6 0.7 1.7 12 12 74 65 10 10 notes: 1. currents are measured at high temperature (100 c junction temperature) and maximum voltage. 2. currents are measured at 125c junction temperature. 3. software default selection highlighted in gray. figure 2-8 ? ac loading table 2-45 ? ac waveforms, measuring points, and capacitive loads input low (v) input high (v) measuring point* (v) c load (pf) 02.51.235 * measuring point = v trip. see table 2-18 on page 2-17 for a complete table of trip points. test point test point enable path datapath 35 pf r = 1 k r to vcci for t lz / t zl / t zls r to gnd for t hz / t zh / t zhs 35 pf for t zh / t zhs / t zl / t zls 5 pf for t hz / t lz
automotive proasic3 dc and switching characteristics 2-34 revision 1 timing characteristics table 2-46 ? 2.5 v lvcmos high slew automotive-case conditions: t j = 135c, worst-case vcc = 1.425 v, worst-case vcci = 2.3 v applicable to advanced i/o banks drive strength speed grade t dout t dp t din t py t eout t zl t zh t lz t hz t zls t zhs units 2 ma std 0.64 9.69 0.05 1.45 0.46 8.76 9.69 1.48 1.25 11.26 12.187 ns -1 0.55 8.24 0.04 1.23 0.39 7.45 8.24 1.48 1.25 9.58 10.367 ns 6 ma std 0.64 5.78 0.05 1.45 0.46 5.63 5.78 1.68 1.62 8.13 8.277 ns -1 0.55 4.91 0.04 1.23 0.39 4. 79 4.91 1.69 1.63 6.92 7.04 ns 12 ma std 0.64 3.98 0.05 1.45 0.46 4.05 3.84 1.82 1.86 6.55 6.338 ns -1 0.55 3.39 0.04 1.23 0.39 3.45 3.27 1.83 1.86 5.58 5.392 ns 16 ma std 0.64 3.75 0.05 1.45 0.46 1.85 1.69 3.76 3.97 3.06 2.926 ns -1 0.55 3.19 0.04 1.23 0.39 1.85 1.69 3.20 3.38 3.06 2.929 ns 24 ma std 0.64 3.45 0.05 1.45 0.46 1.70 1.35 3.84 4.47 2.92 2.585 ns -1 0.55 2.94 0.04 1.23 0.39 1.71 1.35 3.27 3.80 2.92 2.586 ns notes: 1. software default selection highlighted in gray. 2. for specific junction temperature and voltage supply levels, refer to table 2-5 on page 2-5 for derating values. table 2-47 ? 2.5 v lvcmos low slew automotive-case conditions: t j = 135c, worst-case vcc = 1.425 v, worst-case vcci = 2.3 v applicable to advanced i/o banks drive strength speed grade t dout t dp t din t py t eout t zl t zh t lz t hz t zls t zhs units 2 ma std 0.64 12.12 0.05 1.45 0.46 12.54 12.74 1.48 1.19 15.04 15.243 ns -1 0.55 10.31 0.04 1.23 0.39 10.67 10.84 1.48 1.20 12.80 12.966 ns 6 ma std 0.64 8.24 0.05 1.45 0.46 9.07 8.74 1.68 1.57 11.57 11.237 ns -1 0.55 7.01 0.04 1.23 0.39 7.71 7.43 1.69 1.57 9.84 9.559 ns 12 ma std 0.64 6.91 0.05 1.45 0.46 7.04 6.62 1.82 1.80 9.54 9.117 ns -1 0.55 5.88 0.04 1.23 0.39 5.99 5.63 1.83 1.80 8.11 7.756 ns 16 ma std 0.64 6.44 0.05 1.45 0.46 6.56 6.18 1.86 1.86 9.06 8.678 ns -1 0.55 5.48 0.04 1.23 0.39 5.58 5.26 1.86 1.86 7.71 7.382 ns 24 ma std 0.64 6.16 0.05 1.45 0.46 6.15 6.16 1.90 2.10 8.65 8.657 ns -1 0.55 5.24 0.04 1.23 0.39 5.23 5.24 1.90 2.10 7.36 7.364 ns note: for specific junction temperature and voltage supply levels, refer to table 2-5 on page 2-5 for derating values.
automotive proasic3 flash family fpgas revision 1 2-35 table 2-48 ? 2.5 v lvcmos high slew automotive-case conditions: t j = 135c, worst-case vcc = 1.425 v, worst-case vcci = 2.3 v applicable to standard plus i/o banks drive strength speed grade t dout t dp t din t py t eout t zl t zh t lz t hz t zls t zhs units 2 ma std 0.64 9.26 0.05 1.45 0.46 8.28 9.26 1.24 1.12 10.78 11.756 ns -1 0.55 7.87 0.04 1.23 0.39 7. 05 7.87 1.24 1.13 9.17 10 ns 6 ma std 0.64 5.43 0.05 1.45 0.46 5.19 5.43 1.43 1.47 7.69 7.926 ns -1 0.55 4.62 0.04 1.23 0.39 4.42 4.62 1.43 1.47 6.55 6.743 ns 12 ma std 0.64 3.59 0.05 1.45 0.46 3.65 3.51 1.56 1.69 6.15 6.012 ns -1 0.55 3.05 0.04 1.23 0.39 3.11 2.99 1.56 1.69 5.23 5.114 ns notes: 1. software default selection highlighted in gray. 2. for specific junction temperature and voltage supply levels, refer to table 2-5 on page 2-5 for derating values. table 2-49 ? 2.5 v lvcmos low slew automotive-case conditions: t j = 135c, worst-case vcc = 1.425 v, worst-case vcci = 2.3 v applicable to standard plus i/o banks drive strength speed grade t dout t dp t din t py t eout t zl t zh t lz t hz t zls t zhs units 2 ma std 0.64 12.12 0.05 1.45 0.46 11.89 12.12 1.25 1.08 14.39 14.622 ns -1 0.55 10.31 0.04 1.23 0.39 10.12 10.31 1.25 1.08 12.24 12.438 ns 6 ma std 0.64 8.24 0.05 1.45 0.46 8 .39 8.23 1.43 1.42 10.89 10.73 ns -1 0.55 7.01 0.04 1.23 0.39 7.14 7.00 1.43 1.42 9.26 9.128 ns 12 ma std 0.64 6.30 0.05 1.45 0.46 6.41 6.16 1.56 1.63 8.91 8.656 ns -1 0.55 5.35 0.04 1.23 0.39 5.45 5.24 1.56 1.63 7.58 7.364 ns note: for specific junction temperature and voltage supply levels, refer to table 2-5 on page 2-5 for derating values.
automotive proasic3 dc and switching characteristics 2-36 revision 1 table 2-50 ? 2.5 v lvcmos high slew automotive-case conditions: t j = 115c, worst-case vcc = 1.425 v, worst-case vcci = 2.3 v applicable to advanced i/o banks drive strength speed grade t dout t dp t din t py t eout t zl t zh t lz t hz t zls t zhs units 2 ma std 0.63 9.37 0.05 1.40 0.45 8 .47 9.37 1.43 1.21 10.89 11.79 ns -1 0.53 7.97 0.04 1.19 0.38 7.21 7.97 1.43 1.21 9.27 10.03 ns 6 ma std 0.63 5.59 0.05 1.40 0.45 5 .45 5.59 1.63 1.57 7.87 8.01 ns -1 0.53 4.75 0.04 1.19 0.38 4. 63 4.75 1.63 1.57 6.69 6.81 ns 12 ma std 0.63 3.85 0.05 1.40 0.45 3.92 3.71 1.77 1.80 6.34 6.13 ns -1 0.53 3.28 0.04 1.19 0.38 3.34 3.16 1.77 1.80 5.39 5.22 ns 16 ma std 0.63 3.63 0.05 1.40 0.45 1 .79 1.64 3.64 3.84 2.96 2.83 ns -1 0.53 3.08 0.04 1.19 0.38 1. 79 1.64 3.09 3.27 2.96 2.83 ns 24 ma std 0.63 3.34 0.05 1.40 0.45 1 .65 1.31 3.72 4.32 2.82 2.50 ns -1 0.53 2.84 0.04 1.19 0.38 1. 65 1.31 3.16 3.68 2.82 2.50 ns notes: 1. software default selection highlighted in gray. 2. for specific junction temperature and voltage supply levels, refer to table 2-5 on page 2-5 for derating values. table 2-51 ? 2.5 v lvcmos low slew automotive-case conditions: tj = 115c, worst-c ase vcc = 1.425 v, worst-case vcci = 2.3 v applicable to advanced i/o banks drive strength speed grade t dout t dp t din t py t eout t zl t zh t lz t hz t zls t zhs units 2 ma std 0.63 11.73 0.05 1.40 0.45 12 .14 12.33 1.43 1.16 14.55 14.75 ns -1 0.53 9.98 0.04 1.19 0.38 10.3 2 10.49 1.43 1.16 12.38 12.55 ns 6 ma std 0.63 7.97 0.05 1.40 0.45 8.77 8.45 1.63 1.51 11.19 10.87 ns -1 0.53 6.78 0.04 1.19 0.38 7. 46 7.19 1.63 1.52 9.52 9.25 ns 12 ma std 0.63 6.68 0.05 1.40 0.45 6.81 6.40 1.77 1.74 9.23 8.82 ns -1 0.53 5.69 0.04 1.19 0.38 5. 79 5.45 1.77 1.74 7.85 7.50 ns 16 ma std 0.63 6.24 0.05 1.40 0.45 6.35 5.98 1.80 1.80 8.77 8.40 ns -1 0.53 5.30 0.04 1.19 0.38 5. 40 5.08 1.80 1.80 7.46 7.14 ns 24 ma std 0.63 5.96 0.05 1.40 0.45 5.95 5.96 1.84 2.03 8.37 8.38 ns -1 0.53 5.07 0.04 1.19 0.38 5. 06 5.07 1.84 2.03 7.12 7.12 ns note: for specific junction temperature and voltage supply levels, refer to table 2-5 on page 2-5 for derating values.
automotive proasic3 flash family fpgas revision 1 2-37 table 2-52 ? 2.5 v lvcmos high slew automotive-case conditions: tj = 115c, worst-c ase vcc = 1.425 v, worst-case vcci = 2.3 v applicable to standard plus i/o banks drive strength speed grade t dout t dp t din t py t eout t zl t zh t lz t hz t zls t zhs units 2 ma std 0.63 8.95 0.05 1.40 0.45 8 .01 8.95 1.20 1.09 10.43 11.37 ns -1 0.53 7.62 0.04 1.19 0.38 6. 82 7.62 1.20 1.09 8.87 9.68 ns 6 ma std 0.63 5.25 0.05 1.40 0.45 5 .03 5.25 1.38 1.42 7.44 7.67 ns -1 0.53 4.47 0.04 1.19 0.38 4. 27 4.47 1.38 1.42 6.33 6.52 ns 12 ma std 0.63 3.47 0.05 1.40 0.45 3.53 3.40 1.51 1.63 5.95 5.82 ns -1 0.53 2.95 0.04 1.19 0.38 3.01 2.89 1.51 1.63 5.06 4.95 ns notes: 1. software default selection highlighted in gray. 2. for specific junction temperature and voltage supply levels, refer to table 2-5 on page 2-5 for derating values. table 2-53 ? 2.5 v lvcmos low slew automotive-case conditions: t j = 115c, worst-case vcc = 1.425 v, worst-case vcci = 2.3 v applicable to standard plus i/o banks drive strength speed grade t dout t dp t din t py t eout t zl t zh t lz t hz t zls t zhs units 2 ma std 0.63 11.73 0.05 1.40 0.45 11.51 11.73 1.21 1.04 13.93 14.15 ns -1 0.53 9.98 0.04 1.19 0.38 9.79 9.98 1.21 1.04 11.85 12.03 ns 6 ma std 0.63 7.97 0.05 1.40 0.45 8.12 7.96 1.38 1.37 10.54 10.38 ns -1 0.53 6.78 0.04 1.19 0.38 6. 91 6.77 1.39 1.37 8.96 8.83 ns 12 ma std 0.63 6.09 0.05 1.40 0.45 6.20 5.96 1.51 1.58 8.62 8.38 ns -1 0.53 5.18 0.04 1.19 0.38 5. 28 5.07 1.51 1.58 7.33 7.12 ns note: for specific junction temperature and voltage supply levels, refer to table 2-5 on page 2-5 for derating values.
automotive proasic3 dc and switching characteristics 2-38 revision 1 1.8 v lvcmos low-voltage cmos for 1.8 v is an extension of the lvcmos standa rd (jesd8-5) used for general- purpose 1.8 v applications. it uses a 1.8 v input buffer and a push-pull output buffer. table 2-54 ? minimum and maximum dc input and output levels applicable to advanced i/o banks 1.8 v lvcmos vil vih vol voh i ol i oh i osl i osh i il i ih drive strength min. v max. v min. v max. v max. v min. vmama max. ma 1 max. ma 1 a 2 a 2 2 ma ?0.3 0.35 * vcci 0.65 * vcci 3. 6 0.45 vcci ? 0.45 2 2 11 9 10 10 4 ma ?0.3 0.35 * vcci 0.65 * vcci 3.6 0.45 vcci ? 0.45 4 4 22 17 10 10 6 ma ?0.3 0.35 * vcci 0.65 * v cci 3.6 0.45 vcci ? 0.45 6 6 44 35 10 10 8 ma ?0.3 0.35 * vcci 0.65 * vcci 3.6 0.45 vcci ? 0.45 8 8 51 45 10 10 12 ma ?0.3 0.35 * vcci 0.65 * vcci 3.6 0.45 vcci ? 0.45 12 12 74 91 10 10 16 ma ?0.3 0.35 * vcci 0.65 * vcci 3. 6 0.45 vcci ? 0.45 16 16 74 91 10 10 notes: 1. currents are measured at high temperature (100 c junction temperature) and maximum voltage. 2. currents are measured at 125c junction temperature. 3. software default selection highlighted in gray. table 2-55 ? minimum and maximum dc input and output levels applicable to standard plus i/o i/o banks 1.8 v lvcmos vil vih vol voh i ol i oh i osl i osh i il i ih drive strength min. v max. v min. v max. v max. v min. vmama max. ma 1 max. ma 1 a 2 a 2 2 ma ?0.3 0.35 * vcci 0.65 * vcci 3. 6 0.45 vcci ? 0.45 2 2 11 9 10 10 4 ma ?0.3 0.35 * vcci 0.65 * vcci 3.6 0.45 vcci ? 0.45 4 4 22 17 10 10 6 ma ?0.3 0.35 * vcci 0.65 * vcci 3.6 0.45 vcci ? 0.45 6 6 44 35 10 10 8 ma ?0.3 0.35 * vcci 0.65 * vcci 3.6 0.45 vcci ? 0.45 8 8 44 35 10 10 notes: 1. currents are measured at high temperature (100 c junction temperature) and maximum voltage. 2. currents are measured at 125c junction temperature. 3. software default selection highlighted in gray. figure 2-9 ? ac loading table 2-56 ? ac waveforms, measuring points, and capacitive loads input low (v) input high (v) measuring point* (v) c load (pf) 01.80.935 * measuring point = v trip. see table 2-18 on page 2-17 for a complete table of trip points. test point test point enable path datapath 35 pf r = 1 k r to vcci for t lz / t zl / t zls r to gnd for t hz / t zh / t zhs 35 pf for t zh / t zhs / t zl / t zls 5 pf for t hz / t lz
automotive proasic3 flash family fpgas revision 1 2-39 timing characteristics table 2-57 ? 1.8 v lvcmos high slew automotive-case conditions: t j = 135c, worst-case vcc = 1.425 v, worst-case vcci = 2.3 v applicable to advanced i/o banks drive strength speed grade t dout t dp t din t py t eout t zl t zh t lz t hz t zls t zhs units 2 ma std 0.64 13.26 0.05 1.36 0.46 10.22 13.26 1.53 0.90 12.72 15.764 ns -1 0.55 11.28 0.04 1.16 0.39 8.69 11.28 1.53 0.90 10.82 13.41 ns 4 ma std 0.64 7.73 0.05 1.36 0.46 6.55 7.73 1.78 1.54 9.05 10.232 ns -1 0.55 6.58 0.04 1.16 0.39 5.58 6.58 1.78 1.54 7.70 8.704 ns 6 ma std 0.64 4.97 0.05 1.36 0.46 4.67 4.97 1.95 1.83 7.17 7.472 ns -1 0.55 4.23 0.04 1.16 0.39 3.98 4.23 1.95 1.83 6.10 6.356 ns 8 ma std 0.64 4.39 0.05 1.36 0.46 4.39 4.39 1.99 1.91 6.89 6.888 ns -1 0.55 3.73 0.04 1.16 0.39 3.74 3.73 1.99 1.91 5.86 5.859 ns 12 ma std 0.64 3.95 0.05 1.36 0.46 1.95 1.68 4.14 4.56 3.16 2.915 ns -1 0.55 3.36 0.04 1.16 0.39 1.95 1.68 3.52 3.88 3.16 2.918 ns 16 ma std 0.64 3.95 0.05 1.36 0.46 1.95 1.68 4.14 4.56 3.16 2.915 ns -1 0.55 3.36 0.04 1.16 0.39 1.95 1.68 3.52 3.88 3.16 2.918 ns notes: 1. software default selection highlighted in gray. 2. for specific junction temperature and voltage supply levels, refer to table 2-5 on page 2-5 for derating values.
automotive proasic3 dc and switching characteristics 2-40 revision 1 table 2-58 ? 1.8 v lvcmos low slew automotive-case conditions: t j = 135c, worst-case vcc = 1.425 v, worst-case vcci = 2.3 v applicable to advanced i/o banks drive strength speed grade t dout t dp t din t py t eout t zl t zh t lz t hz t zls t zhs units 2 ma std 0.64 17.36 0.05 1.45 0.46 15.78 17.36 1.53 0.87 18.28 19.864 ns -1 0.55 14.77 0.04 1.23 0.39 13.42 14.77 1.54 0.87 15.55 16.897 ns 4 ma std 0.64 11.71 0.05 1.45 0.46 11 .64 11.71 1.78 1.48 14.14 14.214 ns -1 0.55 9.96 0.04 1.23 0.39 9.90 9.96 1.78 1.48 12.03 12.091 ns 6 ma std 0.64 9.00 0.05 1.45 0.46 9.17 8.77 1.95 1.77 11.67 11.267 ns -1 0.55 7.66 0.04 1.23 0.39 7.80 7.46 1.95 1.77 9.92 9.585 ns 8 ma std 0.64 8.39 0.05 1.45 0.46 8.54 8.16 1.99 1.85 11.04 10.66 ns -1 0.55 7.14 0.04 1.23 0.39 7.27 6.94 1.99 1.85 9.40 9.068 ns 12 ma std 0.64 8.15 0.05 1.45 0.46 8.09 8.15 2.05 2.14 10.59 10.654 ns -1 0.55 6.94 0.04 1.23 0.39 6.88 6.94 2.05 2.14 9.01 9.063 ns 16 ma std 0.64 8.15 0.05 1.45 0.46 8.09 8.15 2.05 2.14 10.59 10.654 ns -1 0.55 6.94 0.04 1.23 0.39 6.88 6.94 2.05 2.14 9.01 9.063 ns note: for specific junction temperature and voltage supply levels, refer to table 2-5 on page 2-5 for derating values. table 2-59 ? 1.8 v lvcmos high slew automotive-case conditions: t j = 135c, worst-case vcc = 1.425 v, worst-case vcci = 2.3 v applicable to standard plus i/o banks drive strength speed grade t dout t dp t din t py t eout t zl t zh t lz t hz t zls t zhs units 2 ma std 0.64 13.26 0.05 1.36 0.46 9.75 12.67 1.24 0.82 12.26 15.17 ns -1 0.55 11.28 0.04 1.16 0.39 8.30 10.78 1.24 0.83 10.43 12.905 ns 4 ma std 0.64 7.73 0.05 1.36 0.46 6.13 7.25 1.46 1.41 8.63 9.749 ns -1 0.55 6.58 0.04 1.16 0.39 5. 21 6.17 1.46 1.41 7.34 8.293 ns 6 ma std 0.64 4.97 0.05 1.36 0.46 4.29 4.54 1.62 1.68 6.79 7.039 ns -1 0.55 4.23 0.04 1.16 0.39 3. 65 3.86 1.62 1.68 5.78 5.987 ns 8 ma std 0.64 4.39 0.05 1.36 0.46 4.29 4.54 1.62 1.68 6.79 7.039 ns -1 0.55 3.73 0.04 1.16 0.39 3.65 3.86 1.62 1.68 5.78 5.987 ns notes: 1. software default selection highlighted in gray. 2. for specific junction temperature and voltage supply levels, refer to table 2-5 on page 2-5 for derating values.
automotive proasic3 flash family fpgas revision 1 2-41 table 2-60 ? 1.8 v lvcmos low slew automotive-case conditions: t j = 135c, worst-case vcc = 1.425 v, worst-case vcci = 2.3 v applicable to standard plus i/o banks drive strength speed grade t dout t dp t din t py t eout t zl t zh t lz t hz t zls t zhs units 2 ma std 0.64 17.36 0.05 1.45 0.46 15.09 16.55 1.24 0.79 17.59 19.052 ns -1 0.55 14.77 0.04 1.23 0.39 12.84 14.08 1.24 0.79 14.96 16.207 ns 4 ma std 0.64 11.71 0.05 1.45 0.46 10.88 11.07 1.47 1.35 13.38 13.567 ns -1 0.55 9.96 0.04 1.23 0.39 9.26 9.41 1.47 1.35 11.38 11.541 ns 6 ma std 0.64 9.00 0.05 1.45 0.46 8.47 8.18 1.62 1.62 10.97 10.685 ns -1 0.55 7.66 0.04 1.23 0.39 7.21 6.96 1.62 1.62 9.33 9.089 ns 8 ma std 0.64 8.39 0.05 1.45 0.46 8.47 8.18 1.62 1.62 10.97 10.685 ns -1 0.55 7.14 0.04 1.23 0.39 7.21 6.96 1.62 1.62 9.33 9.089 ns note: for specific junction temperature and voltage supply levels, refer to table 2-5 on page 2-5 for derating values. table 2-61 ? 1.8 v lvcmos high slew automotive-case conditions: t j = 115c, worst-case vcc = 1.425 v, worst-case vcci = 2.3 v applicable to advanced i/o banks drive strength speed grade t dout t dp t din t py t eout t zl t zh t lz t hz t zls t zhs units 2 ma std 0.63 12.83 0.05 1.32 0.45 9.88 12.83 1.48 0.87 12.30 15.25 ns -1 0.53 10.92 0.04 1.12 0.38 8.41 10.92 1.48 0.87 10.46 12.97 ns 4 ma std 0.63 7.48 0.05 1.32 0.45 6.34 7.48 1.72 1.49 8.76 9.90 ns -1 0.53 6.36 0.04 1.12 0.38 5. 39 6.36 1.72 1.49 7.45 8.42 ns 6 ma std 0.63 4.81 0.05 1.32 0.45 4.52 4.81 1.89 1.77 6.94 7.23 ns -1 0.53 4.09 0.04 1.12 0.38 3. 85 4.09 1.89 1.77 5.90 6.15 ns 8 ma std 0.63 4.25 0.05 1.32 0.45 4.25 4.25 1.92 1.85 6.67 6.66 ns -1 0.53 3.61 0.04 1.12 0.38 3. 61 3.61 1.93 1.85 5.67 5.67 ns 12 ma std 0.63 3.82 0.05 1.32 0.45 1.89 1.63 4.00 4.41 3.06 2.82 ns -1 0.53 3.25 0.04 1.12 0.38 1.89 1.63 3.41 3.75 3.06 2.82 ns 16 ma std 0.63 3.82 0.05 1.32 0.45 1.89 1.63 4.00 4.41 3.06 2.82 ns -1 0.53 3.25 0.04 1.12 0.38 1. 89 1.63 3.41 3.75 3.06 2.82 ns notes: 1. software default selection highlighted in gray. 2. for specific junction temperature and voltage supply levels, refer to table 2-5 on page 2-5 for derating values.
automotive proasic3 dc and switching characteristics 2-42 revision 1 table 2-62 ? 1.8 v lvcmos low slew automotive-case conditions: t j = 115c, worst-case vcc = 1.425 v, worst-case vcci = 2.3 v applicable to advanced i/o banks drive strength speed grade t dout t dp t din t py t eout t zl t zh t lz t hz t zls t zhs units 2 ma std 0.63 16.80 0.05 1.40 0.45 15 .27 16.80 1.48 0.84 17.69 19.22 ns -1 0.53 14.29 0.04 1.19 0.38 12.99 14.29 1.49 0.84 15.05 16.35 ns 4 ma std 0.63 11.33 0.05 1.40 0.45 11.26 11.33 1.73 1.43 13.68 13.75 ns -1 0.53 9.64 0.04 1.19 0.38 9.58 9.64 1.73 1.43 11.64 11.70 ns 6 ma std 0.63 8.71 0.05 1.40 0.45 8.87 8.48 1.89 1.72 11.29 10.90 ns -1 0.53 7.41 0.04 1.19 0.38 7. 54 7.22 1.89 1.72 9.60 9.27 ns 8 ma std 0.63 8.12 0.05 1.40 0.45 8.27 7.89 1.93 1.79 10.69 10.31 ns -1 0.53 6.90 0.04 1.19 0.38 7. 03 6.72 1.93 1.79 9.09 8.77 ns 12 ma std 0.63 7.89 0.05 1.40 0.45 7.83 7.89 1.98 2.07 10.25 10.31 ns -1 0.53 6.71 0.04 1.19 0.38 6. 66 6.71 1.98 2.07 8.72 8.77 ns 16 ma std 0.63 7.89 0.05 1.40 0.45 7.83 7.89 1.98 2.07 10.25 10.31 ns -1 0.53 6.71 0.04 1.19 0.38 6. 66 6.71 1.98 2.07 8.72 8.77 ns note: for specific junction temperature and voltage supply levels, refer to table 2-5 on page 2-5 for derating values. table 2-63 ? 1.8 v lvcmos high slew automotive-case conditions: t j = 115c, worst-case vcc = 1.425 v, worst-case vcci = 2.3 v applicable to standard plus i/o banks drive strength speed grade t dout t dp t din t py t eout t zl t zh t lz t hz t zls t zhs units 2 ma std 0.63 12.83 0.05 1.32 0.45 9.44 12.26 1.20 0.80 11.86 14.68 ns -1 0.53 10.92 0.04 1.12 0.38 8.03 10.43 1.20 0.80 10.09 12.49 ns 4 ma std 0.63 7.48 0.05 1.32 0.45 5.93 7.01 1.41 1.36 8.35 9.43 ns -1 0.53 6.36 0.04 1.12 0.38 5. 04 5.97 1.42 1.37 7.10 8.02 ns 6 ma std 0.63 4.81 0.05 1.32 0.45 4.15 4.39 1.57 1.63 6.57 6.81 ns -1 0.53 4.09 0.04 1.12 0.38 3. 53 3.74 1.57 1.63 5.59 5.79 ns 8 ma std 0.63 4.25 0.05 1.32 0.45 4.15 4.39 1.57 1.63 6.57 6.81 ns -1 0.53 3.61 0.04 1.12 0.38 3.53 3.74 1.57 1.63 5.59 5.79 ns notes: 1. software default selection highlighted in gray. 2. for specific junction temperature and voltage supply levels, refer to table 2-5 on page 2-5 for derating values.
automotive proasic3 flash family fpgas revision 1 2-43 1.5 v lvcmos (jesd8-11) low-voltage cmos for 1.5 v is an extension of the lvcmos standard (jesd8-5) used for general- purpose 1.5 v applications. it uses a 1.5 v input buffer and a push-pull output buffer. table 2-64 ? 1.8 v lvcmos low slew automotive-case conditions: t j = 115c, worst-case vcc = 1.425 v, worst-case vcci = 2.3 v applicable to standard plus i/o banks drive strength speed grade t dout t dp t din t py t eout t zl t zh t lz t hz t zls t zhs units 2 ma std 0.63 16.80 0.05 1.40 0.45 14 .60 16.01 1.20 0.77 17.02 18.43 ns -1 0.53 14.29 0.04 1.19 0.38 12.42 13.62 1.20 0.77 14.48 15.68 ns 4 ma std 0.63 11.33 0.05 1.40 0.45 10 .53 10.71 1.42 1.31 12.95 13.13 ns -1 0.53 9.64 0.04 1.19 0.38 8.96 9.11 1.42 1.31 11.01 11.17 ns 6 ma std 0.63 8.71 0.05 1.40 0.45 8.19 7.92 1.57 1.57 10.61 10.34 ns -1 0.53 7.41 0.04 1.19 0.38 6. 97 6.74 1.57 1.57 9.03 8.79 ns 8 ma std 0.63 8.12 0.05 1.40 0.45 8.19 7.92 1.57 1.57 10.61 10.34 ns -1 0.53 6.90 0.04 1.19 0.38 6. 97 6.74 1.57 1.57 9.03 8.79 ns note: for specific junction temperature and voltage supply levels, refer to table 2-5 on page 2-5 for derating values. table 2-65 ? minimum and maximum dc input and output levels applicable to advanced i/o banks 1.5 v lvcmos vil vih vol voh i ol i oh i osl i osh i il i ih drive strength min. v max. v min. v max. v max. v min. vmama max. ma 1 max. ma 1 a 2 a 2 2 ma ?0.3 0.30 * vcci 0.7 * vcci 3.6 0.25 * vcci 0.75 * vcci 2 2 16 13 10 10 4 ma ?0.3 0.30 * vcci 0.7 * v cci 3.6 0.25 * vcci 0.75 * vcci 4 4 33 25 10 10 6 ma ?0.3 0.30 * vcci 0.7 * vcci 3.6 0.25 * vcci 0.75 * vcci 6 6 39 32 10 10 8 ma ?0.3 0.30 * vcci 0.7 * vcci 3.6 0.25 * vcci 0.75 * vcci 8 8 55 66 10 10 12 ma ?0.3 0.30 * vcci 0.7 * vcci 3.6 0.25 * vcci 0.75 * v cci 12 12 55 66 10 10 notes: 1. currents are measured at high temperature (100 c junction temperature) and maximum voltage. 2. currents are measured at 125c junction temperature. 3. software default selection highlighted in gray.
automotive proasic3 dc and switching characteristics 2-44 revision 1 table 2-66 ? minimum and maximum dc input and output levels applicable to standard plus i/o banks 1.5 v lvcmos vil vih vol voh i ol i oh i osl i osh i il i ih drive strength min. v max. v min. v max. v max. v min. vmama max. ma 1 max. ma 1 a 2 a 2 2 ma ?0.3 0.30 * vcci 0.7 * vcci 3.6 0.25 * vcci 0.75 * vcci 2 2 0 0 10 10 4 ma ?0.3 0.30 * vcci 0.7 * vcci 3.6 0.25 * vcci 0.75 * vcci 4 4 0 0 10 10 notes: 1. currents are measured at high temperature (100 c junction temperature) and maximum voltage. 2. currents are measured at 125c junction temperature. 3. software default selection highlighted in gray. figure 2-10 ? ac loading table 2-67 ? ac waveforms, measuring points, and capacitive loads input low (v) input high (v) measuring point* (v) c load (pf) 0 1.5 0.75 35 * measuring point = v trip. see table 2-18 on page 2-17 for a complete table of trip points. test point test point enable path datapath 35 pf r = 1 k r to vcci for t lz / t zl / t zls r to gnd for t hz / t zh / t zhs 35 pf for t zh / t zhs / t zl / t zls 5 pf for t hz / t lz
automotive proasic3 flash family fpgas revision 1 2-45 timing characteristics table 2-68 ? 1.5 v lvcmos high slew automotive-case conditions: t j = 135c, worst-case vcc = 1.425 v, worst-case vcci = 2.3 v applicable to advanced i/o banks drive strength speed grade t dout t dp t din t py t eout t zl t zh t lz t hz t zls t zhs units 2 ma std 0.64 9.35 0.05 1.61 0.46 7.63 9.35 1.87 1.50 10.13 11.851 ns -1 0.55 7.95 0.04 1.37 0.39 6.49 7.95 1.87 1.50 8.62 10.081 ns 4 ma std 0.64 5.94 0.05 1.61 0.46 5.42 5.94 2.07 1.84 7.92 8.442 ns -1 0.55 5.05 0.04 1.37 0.39 4.61 5.05 2.07 1.85 6.74 7.181 ns 6 ma std 0.64 5.22 0.05 1.61 0.46 5.09 5.22 2.11 1.93 7.59 7.718 ns -1 0.55 4.44 0.04 1.37 0.39 4.33 4.44 2.11 1.93 6.45 6.566 ns 8 ma std 0.64 4.56 0.05 1.61 0.46 2.25 1.98 4.41 4.70 3.46 3.211 ns -1 0.55 3.88 0.04 1.37 0.39 2.25 1.98 3.75 4.00 3.46 3.213 ns 12 ma std 0.64 4.56 0.05 1.61 0.46 2.25 1.98 4.41 4.70 3.46 3.211 ns -1 0.55 3.88 0.04 1.37 0.39 2.25 1.98 3.75 4.00 3.46 3.213 ns notes: 1. software default selection highlighted in gray. 2. for specific junction temperature and voltage supply levels, refer to table 2-5 on page 2-5 for derating values. table 2-69 ? 1.5 v lvcmos low slew automotive-case conditions: t j = 135c, worst-case vcc = 1.425 v, worst-case vcci = 2.3 v applicable to advanced i/o banks drive strength speed grade t dout t dp t din t py t eout t zl t zh t lz t hz t zls t zhs units 2 ma std 0.64 14.29 0.05 1.45 0.46 14.32 14.29 1.88 1.43 16.82 16.794 ns -1 0.55 12.16 0.04 1.23 0.39 12.18 12.16 1.88 1.43 14.31 14.286 ns 4 ma std 0.64 11.19 0.05 1.45 0.46 11 .40 10.67 2.07 1.77 13.90 13.175 ns -1 0.55 9.52 0.04 1.23 0.39 9.70 9.08 2.07 1.77 11.82 11.207 ns 6 ma std 0.64 10.44 0.05 1.45 0.46 10. 63 9.94 2.12 1.86 13.13 12.442 ns -1 0.55 8.88 0.04 1.23 0.39 9.04 8.46 2.12 1.86 11.17 10.584 ns 8 ma std 0.64 9.96 0.05 1.45 0.46 10.15 9.94 2.18 2.19 12.65 12.445 ns -1 0.55 8.47 0.04 1.23 0.39 8.63 8.46 2.19 2.20 10.76 10.586 ns 12 ma std 0.64 9.96 0.05 1.45 0.46 10.15 9.94 2.18 2.19 12.65 12.445 ns -1 0.55 8.47 0.04 1.23 0.39 8.63 8.46 2.19 2.20 10.76 10.586 ns note: for specific junction temperature and voltage supply levels, refer to table 2-5 on page 2-5 for derating values.
automotive proasic3 dc and switching characteristics 2-46 revision 1 table 2-70 ? 1.5 v lvcmos high slew automotive-case conditions: t j = 135c, worst-case vcc = 1.425 v, worst-case vcci = 2.3 v applicable to standard plus i/o banks drive strength speed grade t dout t dp t din t py t eout t zl t zh t lz t hz t zls t zhs units 2 ma std 0.64 8.76 0.05 1.59 0.46 7.63 9.35 1.87 1.50 10.13 11.851 ns -1 0.55 7.45 0.04 1.35 0.39 6.49 7.95 1.87 1.50 8.62 10.081 ns 4 ma std 0.64 5.41 0.05 1.59 0.46 5.42 5.94 2.07 1.84 7.92 8.442 ns -1 0.55 4.60 0.04 1.35 0.39 4.61 5.05 2.07 1.85 6.74 7.181 ns notes: 1. software default selection highlighted in gray. 2. for specific junction temperature and voltage supply levels, refer to table 2-5 on page 2-5 for derating values. table 2-71 ? 1.5 v lvcmos low slew automotive-case conditions: t j = 135c, worst-case vcc = 1.425 v, worst-case vcci = 2.3 v applicable to standard plus i/o banks drive strength speed grade t dout t dp t din t py t eout t zl t zh t lz t hz t zls t zhs units 2 ma std 0.64 13.51 0.05 1.45 0.46 14.32 14.29 1.88 1.43 16.82 16.794 ns -1 0.55 11.49 0.04 1.23 0.39 12.18 12.16 1.88 1.43 14.31 14.286 ns 4 ma std 0.64 10.38 0.05 1.45 0.46 11.40 10.67 2.07 1.77 13.90 13.175 ns -1 0.55 8.83 0.04 1.23 0.39 9.70 9.08 2.07 1.77 11.82 11.207 ns note: for specific junction temperature and voltage supply levels, refer to table 2-5 on page 2-5 for derating values. table 2-72 ? 1.5 v lvcmos high slew automotive-case conditions: t j = 115c, worst-case vcc = 1.425 v, worst-case vcci = 2.3 v applicable to advanced i/o banks drive strength speed grade t dout t dp t din t py t eout t zl t zh t lz t hz t zls t zhs units 2 ma std 0.63 9.05 0.05 1.56 0.45 7.38 9.05 1.81 1.45 9.80 11.47 ns -1 0.53 7.70 0.04 1.32 0.38 6. 28 7.70 1.81 1.45 8.34 9.75 ns 4 ma std 0.63 5.75 0.05 1.56 0.45 5.25 5.75 2.00 1.78 7.67 8.17 ns -1 0.53 4.89 0.04 1.32 0.38 4. 46 4.89 2.00 1.78 6.52 6.95 ns 6 ma std 0.63 5.05 0.05 1.56 0.45 4.92 5.05 2.04 1.87 7.34 7.47 ns -1 0.53 4.29 0.04 1.32 0.38 4. 19 4.29 2.04 1.87 6.24 6.35 ns 8 ma std 0.63 4.41 0.05 1.56 0.45 2.18 1.91 4.27 4.55 3.35 3.11 ns -1 0.53 3.75 0.04 1.32 0.38 2. 18 1.91 3.63 3.87 3.35 3.11 ns 12 ma std 0.63 4.41 0.05 1.56 0.45 2.18 1.91 4.27 4.55 3.35 3.11 ns -1 0.53 3.75 0.04 1.32 0.38 2.18 1.91 3.63 3.87 3.35 3.11 ns notes: 1. software default selection highlighted in gray. 2. for specific junction temperature and voltage supply levels, refer to table 2-5 on page 2-5 for derating values.
automotive proasic3 flash family fpgas revision 1 2-47 table 2-73 ? 1.5 v lvcmos low slew automotive-case conditions: t j = 115c, worst-case vcc = 1.425 v, worst-case vcci = 2.3 v applicable to advanced i/o banks drive strength speed grade t dout t dp t din t py t eout t zl t zh t lz t hz t zls t zhs units 2 ma std 0.63 13.83 0.05 1.40 0.45 13 .86 13.83 1.82 1.39 16.28 16.25 ns -1 0.53 11.76 0.04 1.19 0.38 11.79 11.76 1.82 1.39 13.85 13.82 ns 4 ma std 0.63 10.83 0.05 1.40 0.45 11.03 10.33 2.00 1.71 13.45 12.75 ns -1 0.53 9.21 0.04 1.19 0.38 9.38 8.79 2.01 1.72 11.44 10.84 ns 6 ma std 0.63 10.10 0.05 1.40 0.45 10.28 9.62 2.05 1.80 12.70 12.04 ns -1 0.53 8.59 0.04 1.19 0.38 8.75 8.18 2.05 1.80 10.81 10.24 ns 8 ma std 0.63 9.64 0.05 1.40 0.45 9.82 9.62 2.11 2.12 12.23 12.04 ns -1 0.53 8.20 0.04 1.19 0.38 8.35 8.18 2.11 2.12 10.41 10.24 ns 12 ma std 0.63 9.64 0.05 1.40 0.45 9.82 9.62 2.11 2.12 12.23 12.04 ns -1 0.53 8.20 0.04 1.19 0.38 8.35 8.18 2.11 2.12 10.41 10.24 ns note: for specific junction temperature and voltage supply levels, refer to table 2-5 on page 2-5 for derating values. table 2-74 ? 1.5 v lvcmos high slew automotive-case conditions: t j = 115c, worst-case vcc = 1.425 v, worst-case vcci = 2.3 v applicable to standard plus i/o banks drive strength speed grade t dout t dp t din t py t eout t zl t zh t lz t hz t zls t zhs units 2 ma std 0.63 8.47 0.05 1.54 0.45 7.38 9.05 1.81 1.45 9.80 11.47 ns -1 0.53 7.21 0.04 1.31 0.38 6. 28 7.70 1.81 1.45 8.34 9.75 ns 4 ma std 0.63 5.24 0.05 1.54 0.45 5.25 5.75 2.00 1.78 7.67 8.17 ns -1 0.53 4.45 0.04 1.31 0.38 4.46 4.89 2.00 1.78 6.52 6.95 ns notes: 1. software default selection highlighted in gray. 2. for specific junction temperature and voltage supply levels, refer to table 2-5 on page 2-5 for derating values. table 2-75 ? 1.5 v lvcmos low slew automotive-case conditions: t j = 115c, worst-case vcc = 1.425 v, worst-case vcci = 2.3 v applicable to standard plus i/o banks drive strength speed grade t dout t dp t din t py t eout t zl t zh t lz t hz t zls t zhs units 2 ma std 0.63 13.07 0.05 1.40 0.45 13 .86 13.83 1.82 1.39 16.28 16.25 ns -1 0.53 11.12 0.04 1.19 0.38 11.79 11.76 1.82 1.39 13.85 13.82 ns 4 ma std 0.63 10.04 0.05 1.40 0.45 11.03 10.33 2.00 1.71 13.45 12.75 ns -1 0.53 8.54 0.04 1.19 0.38 9.38 8.79 2.01 1.72 11.44 10.84 ns note: for specific junction temperature and voltage supply levels, refer to table 2-5 on page 2-5 for derating values.
automotive proasic3 dc and switching characteristics 2-48 revision 1 3.3 v pci, 3.3 v pci-x the peripheral component interface for 3.3 v standard specifies support for 33 mhz and 66 mhz pci bus applications. ac loadings are defined per the pci/ pci-x specifications for the datapath; actel loadings for enable path characterization are described in figure 2-11 . ac loadings are defined per pci/pci -x specifications for the datapath; actel loading for tristate is described in ta b l e 2 - 7 7 . timing characteristics table 2-76 ? minimum and maximum dc input and output levels 3.3 v pci/pci-x vil vih vol voh i ol i oh i osl i osh i il i ih drive strength min. v max. v min. v max. v max. v min. vmama max. ma 1 max. ma 1 a 2 a 2 per pci specification per pci curves 10 10 notes: 1. currents are measured at high temperature (100 c junction temperature) and maximum voltage. 2. currents are measured at 125c junction temperature. figure 2-11 ? ac loading test point enable path r to vcci for t lz / t zl / t zls 10 pf for t zh / t zhs / t zl / t zls 5 pf for t hz / t lz r to gnd for t hz / t zh / t zhs r = 1 k test point datapath r = 25 r to vcci for t dp (f) r to gnd for t dp (r) table 2-77 ? ac waveforms, measuring points, and capacitive loads input low (v) input high (v) measuring point* (v) c load (pf) 0 3.3 0.285 * vcci for tdp(r) 0.615 * vcci for tdp(f) 10 * measuring point = v trip. see table 2-18 on page 2-17 for a complete table of trip points. table 2-78 ? 3.3 v pci/pci-x automotive-case conditions: t j = 135c, worst-case vcc = 1.425 v, worst-case vcci = 3.0 v applicable to advanced i/o banks speed grade t dout t dp t din t py t eout t zl t zh t lz t hz t zls t zhs units std. 0.64 2.58 0.05 0.95 0.46 1. 27 0.94 3.12 3.60 2.49 2.18 ns ?1 0.55 2.19 0.04 0.81 0.39 1.27 0.94 2.65 3.06 2.49 2.18 ns note: for specific junction temperature and voltage supply levels, refer to table 2-5 on page 2-5 for derating values. table 2-79 ? 3.3 v pci/pci-x automotive-case conditions: t j = 135c, worst-case vcc = 1.425 v, worst-case vcci = 3.0 v applicable to standard plus i/o banks speed grade t dout t dp t din t py t eout t zl t zh t lz t hz t zls t zhs units std. 0.64 3.00 0.05 0.93 0.46 1. 27 0.94 3.12 3.60 2.49 2.18 ns ?1 0.55 2.55 0.04 0.79 0.39 1.27 0.94 2.65 3.06 2.49 2.18 ns note: for specific junction temperature and voltage supply levels, refer to table 2-5 on page 2-5 for derating values.
automotive proasic3 flash family fpgas revision 1 2-49 differential i/o characteristics physical implementation configuration of the i/o modules as a differential pa ir is handled by actel designer software when the user instantiates a differential i/o macro in the design. differential i/os can also be used in conjuncti on with the embedded input r egister (inreg), output register (outreg), enable register (enreg), an d double data rate (ddr). however, there is no support for bidirectional i/os or tristates with the lvpecl standards. lvds low-voltage differential signaling (ansi/tia/eia-644 ) is a high-speed, differential i/o standard. it requires that one data bit be carried through two si gnal lines, so two pins are needed. it also requires external resistor termination. the full implementation of the lvds transmitte r and receiver is shown in an example in figure 2-12 on page 2-50 . the building blocks of the lvds transmitter-re ceiver are one transmitter macro, one receiver macro, three board resistors at the transmitter end, and one resistor at the receiver end. the values for the three driver resistors are different from those used in the lvpecl implementation because the output standard specifications are different. along with lvds i/o, proasic3 also supports bu s lvds structure and multipoint lvds (m-lvds) configuration (up to 40 nodes). table 2-80 ? 3.3 v pci/pci-x automotive-case conditions: t j = 115c, worst-case vcc = 1.425 v, worst-case vcci = 3.0 v applicable to advanced i/o banks speed grade t dout t dp t din t py t eout t zl t zh t lz t hz t zls t zhs units std. 0.628 2.50 0.05 0.92 0.45 1.23 0.91 3.02 3.48 2.40 2.11 ns ?1 0.53 2.12 0.04 0.78 0.38 1.23 0.91 2.57 2.96 2.41 2.11 ns note: for specific junction temperature and voltage supply levels, refer to table 2-5 on page 2-5 for derating values. table 2-81 ? 3.3 v pci/pci-x automotive-case conditions: t j = 115c, worst-case vcc = 1.425 v, worst-case vcci = 3.0 v applicable to standard plus i/o banks speed grade t dout t dp t din t py t eout t zl t zh t lz t hz t zls t zhs units std. 0.628 2.90 0.05 0.90 0.45 1.23 0.91 3.02 3.48 2.40 2.11 ns ?1 0.53 2.47 0.04 0.77 0.38 1.23 0.91 2.57 2.96 2.41 2.11 ns note: for specific junction temperature and voltage supply levels, refer to table 2-5 on page 2-5 for derating values.
automotive proasic3 dc and switching characteristics 2-50 revision 1 timing characteristics figure 2-12 ? lvds circuit diag ram and board-level implementation table 2-82 ? minimum and maximum dc input and output levels dc parameter description min. typ. max. units vcci supply voltage 2.375 2.5 2.625 v vol output low voltage 0.9 1.075 1.25 v voh output high voltage 1.25 1.425 1.6 v vi input voltage 0 ? 2.925 v v odiff differential output voltage 250 350 450 mv v ocm output common-mode voltage 1.125 1.25 1.375 v v icm input common-mode voltage 0.05 1.25 2.35 v v idiff input differential voltage 100 350 ? mv notes: 1. 5% 2. differential input voltage = 350 mv table 2-83 ? ac waveforms, measuring points, and capacitive loads input low (v) input high (v) measuring point* (v) 1.075 1.325 cross point * measuring point = v trip. see table 2-18 on page 2-17 for a complete tabl e of trip points. 140 100 z 0 = 50 z 0 = 50 165 165 + ? p n p n inbuf_lvds outbuf_lvds fpga fpga bourns part number: cat16-lv4f12 table 2-84 ? lvds automotive-case conditions: t j = 135c, worst-case vcc = 1.425 v, worst-case vcci = 2.3 v speed grade t dout t dp t din t py units std. 0.64 2.05 0.05 1.79 ns ?1 0.55 1.74 0.04 1.52 ns note: for specific junction temperature and voltage supply levels, refer to table 2-5 on page 2-5 for derating values. table 2-85 ? lvds automotive-case conditions: t j = 115c, worst-case vcc = 1.425 v, worst-case vcci = 2.3 v speed grade t dout t dp t din t py units std. 0.63 1.98 0.05 1.73 ns ?1 0.53 1.68 0.04 1.47 ns note: for specific junction temperature and voltage supply levels, refer to table 2-5 on page 2-5 for derating values.
automotive proasic3 flash family fpgas revision 1 2-51 b-lvds/m-lvds bus lvds (b-lvds) and multipoint lvds (m-lvds) s pecifications extend the existing lvds standard to high-performance multipoint bus applications. multid rop and multipoint bus configurations may contain any combination of drivers, receiv ers, and transceivers. actel lvds drivers provide the higher drive current required by b-lvds and m-lvds to accomm odate the loading. the drivers require series terminations for better signal quality and to control voltage swing. termination is also required at both ends of the bus since the driver can be located anywhere on the bus. these configurations can be implemented using the tribuf_lvds and bibuf_lvds macros along with appr opriate terminations. multipoint designs using actel lvds macros can achieve up to 200 mhz with a maximum of 20 loads. a sample application is given in figure 2-13 . the input and output buffer delays are available in the lvds section in table 2-84 on page 2-50 . example: for a bus consisting of 20 equidistant lo ads, the following terminations provide the required differential voltage, in worst-case industrial operating conditions, at the farthest receiver: r s =60 and r t =70 , given z 0 =50 (2") and z stub =50 (~1.5"). lvpecl low-voltage positive emitter-coupled logic (lvpecl) is another differ ential i/o standard. it requires that one data bit be carried through two signal lines . like lvds, two pins are needed. it also requires external resistor termination. the full implementation of the lvds transmitte r and receiver is shown in an example in figure 2-14 on page 2-52 . the building blocks of the l vpecl transmitter-receiver are one transmitter macro, one receiver macro, three board resistors at the transmi tter end, and one resistor at the receiver end. the values for the three driver resistors are different from those used in the lvds implementation because the output standard specifications are different. figure 2-13 ? b-lvds/m-lvds multipoint application using lvds i/o buffers ... r t r t bibuf_lvds r + - t + - r + - t + - d + - en en en en en receiver transceiver receiver transceiver driver r s r s r s r s r s r s r s r s r s r s z stub z stub z stub z stub z stub z stub z stub z stub z 0 z 0 z 0 z 0 z 0 z 0 z 0 z 0 z 0 z 0 z 0 z 0
automotive proasic3 dc and switching characteristics 2-52 revision 1 timing characteristics figure 2-14 ? lvpecl circuit diagram and board-level im plementation table 2-86 ? minimum and maximum dc input and output levels dc parameter description min. max. min. max. min. max. units v cci supply voltage 3.0 3.3 3.6 v v ol output low voltage 0.96 1.27 1.06 1.43 1.30 1.57 v v oh output high voltage 1.8 2.11 1.92 2.28 2.13 2.41 v v il , v ih input low, input high voltages 0 3.3 0 3.6 0 3.9 v v odiff differential output voltage 0.625 0.97 0.625 0.97 0.625 0.97 v v ocm output common-mode voltage 1.762 1.98 1.762 1.98 1.762 1.98 v v icm input common-mode voltage 1.01 2.57 1.01 2.57 1.01 2.57 v v idiff input differential voltage 300 300 300 mv table 2-87 ? ac waveforms, measuring points, and capacitive loads input low (v) input high (v) measuring point* (v) 1.64 1.94 cross point * measuring point = v trip. see table 2-18 on page 2-17 for a complete table of trip points. 187 w 100 z 0 = 50 z 0 = 50 100 100 + ? p n p n inbuf_lvpecl outbuf_lvpecl fpga fpga bourns part number: cat16-pc4f12 table 2-88 ? lvpecl automotive-case conditions: t j = 135c, worst-case vcc = 1.425 v, worst-case vcci = 3.0 v speed grade t dout t dp t din t py units std. 0.64 2.01 0.05 1.57 ns ?1 0.55 1.71 0.04 1.34 ns note: for specific junction temperature and voltage supply levels, refer to table 2-5 on page 2-5 for derating values. table 2-89 ? lvpecl automotive-case conditions: t j = 115c, worst-case vcc = 1.425 v, worst-case vcci = 3.0 v speed grade t dout t dp t din t py units std. 0.63 1.95 0.05 1.52 ns ?1 0.53 1.66 0.04 1.29 ns note: for specific junction temperature and voltage supply levels, refer to table 2-5 on page 2-5 for derating values.
automotive proasic3 flash family fpgas revision 1 2-53 i/o register specifications fully registered i/o buffers with synchronous enable and asynchronous preset figure 2-15 ? timing model of registered i/o buffers with synchronous enable and asynchronous preset inbuf inbuf inbuf tribuf clkbuf inbuf inbuf clkbuf data input i/o register with: active high enable active high preset positive-edge triggered data output register and enable output register with: active high enable active high preset postive-edge triggered pad out clk enable preset data_out data eout dout enable clk dq dfn1e1p1 pre dq dfn1e1p1 pre dq dfn1e1p1 pre d_enable a b c d e e e e f g h i j l k y core array
automotive proasic3 dc and switching characteristics 2-54 revision 1 table 2-90 ? parameter definition and measuring nodes parameter name parameter definition measuring nodes (from, to)* t oclkq clock-to-q of the output data register h, dout t osud data setup time for the output data register f, h t ohd data hold time for the output data register f, h t osue enable setup time for the output data register g, h t ohe enable hold time for the output data register g, h t opre2q asynchronous preset-to-q of the output data register l, dout t orempre asynchronous preset removal time for the output data register l, h t orecpre asynchronous preset recovery time for the output data register l, h t oeclkq clock-to-q of the output enable register h, eout t oesud data setup time for the output enable register j, h t oehd data hold time for the output enable register j, h t oesue enable setup time for the output enable register k, h t oehe enable hold time for the output enable register k, h t oepre2q asynchronous preset-to-q of the output enable register i, eout t oerempre asynchronous preset removal time for the output enable register i, h t oerecpre asynchronous preset recovery time for the output enable register i, h t iclkq clock-to-q of the input data register a, e t isud data setup time for the input data register c, a t ihd data hold time for the input data register c, a t isue enable setup time for the input data register b, a t ihe enable hold time for the input data register b, a t ipre2q asynchronous preset-to-q of th e input data register d, e t irempre asynchronous preset removal time for the input data register d, a t irecpre asynchronous preset recovery time for the input data register d, a * see figure 2-15 on page 2-53 for more information.
automotive proasic3 flash family fpgas revision 1 2-55 fully registered i/o buffers with synchronous enable and asynchronous clear figure 2-16 ? timing model of the registered i/o buffers with synchronous enable and asynchronous clear enable clk pad out clk enable clr data_out data y aa eout dout core array dq dfn1e1c1 e clr dq dfn1e1c1 e clr dq dfn1e1c1 e clr d_enable bb cc dd ee ff gg ll hh jj kk clkbuf inbuf inbuf tribuf inbuf inbuf clkbuf inbuf data input i/o register with active high enable active high clear positive-edge triggered data output register and enable output register with active high enable active high clear positive-edge triggered
automotive proasic3 dc and switching characteristics 2-56 revision 1 table 2-91 ? parameter definitions and measuring nodes parameter name parameter definition measuring nodes (from, to)* t oclkq clock-to-q of the output data register hh, dout t osud data setup time for the output data register ff, hh t ohd data hold time for the output data register ff, hh t osue enable setup time for the output data register gg, hh t ohe enable hold time for the output data register gg, hh t oclr2q asynchronous clear-to-q of the output data register ll, dout t oremclr asynchronous clear removal time for the output data register ll, hh t orecclr asynchronous clear recovery time for the output data register ll, hh t oeclkq clock-to-q of the output enable register hh, eout t oesud data setup time for the ou tput enable register jj, hh t oehd data hold time for the output enable register jj, hh t oesue enable setup time for the output enable register kk, hh t oehe enable hold time for the output enable register kk, hh t oeclr2q asynchronous clear-to-q of the output enable register ii, eout t oeremclr asynchronous clear removal time fo r the output enable register ii, hh t oerecclr asynchronous clear recovery time for the output enable register ii, hh t iclkq clock-to-q of the input data register aa, ee t isud data setup time for the input data register cc, aa t ihd data hold time for the input data register cc, aa t isue enable setup time for the input data register bb, aa t ihe enable hold time for the input data register bb, aa t iclr2q asynchronous clear-to-q of the input data register dd, ee t iremclr asynchronous clear removal time for the input data register dd, aa t irecclr asynchronous clear recovery time for the input data register dd, aa * see figure 2-16 on page 2-55 for more information.
automotive proasic3 flash family fpgas revision 1 2-57 input register timing characteristics figure 2-17 ? input register timing diagram 50% preset clear out_1 clk data enable t isue 50% 50% t isud t ihd 50% 50% t iclkq 1 0 t ihe t irecpre t irempre t irecclr t iremclr t iwclr t iwpre t ipre2q t iclr2q t ickmpwh t ickmpwl 50% 50% 50% 50% 50% 50% 50% 50% 50% 50% 50% 50% 50% 50% table 2-92 ? input data register propagation delays automotive-case conditions: t j = 135c, worst-case vcc = 1.425 v parameter description ?1 std. units t iclkq clock-to-q of the input da ta register 0.29 0.34 ns t isud data setup time for the input data register 0.32 0.38 ns t ihd data hold time for the input data register 0.00 0.00 ns t isue enable setup time for the input data register 0.45 0.53 ns t ihe enable hold time for the input data register 0.00 0.00 ns t iclr2q asynchronous clear-to-q of the input data register 0.55 0.65 ns t ipre2q asynchronous preset-to-q of the input data register 0.55 0.65 ns t iremclr asynchronous clear removal time fo r the input data register 0.00 0.00 ns t irecclr asynchronous clear recovery time fo r the input data register 0.27 0.32 ns t irempre asynchronous preset removal time fo r the input data register 0.00 0.00 ns t irecpre asynchronous preset recovery time for the input data register 0.27 0.32 ns t iwclr asynchronous clear minimum pulse width for the input data register 0.25 0.30 ns t iwpre asynchronous preset minimum pulse width for the input data register 0.25 0.30 ns t ickmpwh clock minimum pulse width high for the input data register 0.41 0.48 ns t ickmpwl clock minimum pulse width low for the input data register 0.37 0.43 ns note: for specific junction temperature and voltage supply levels, refer to table 2-5 on page 2-5 for derating values.
automotive proasic3 dc and switching characteristics 2-58 revision 1 table 2-93 ? input data register propagation delays automotive-case conditions: t j = 115c, worst-case vcc = 1.425 v parameter description ?1 std. units t iclkq clock-to-q of the input da ta register 0.29 0.34 ns t isud data setup time for the input data register 0.31 0.37 ns t ihd data hold time for the input data register 0.00 0.00 ns t isue enable setup time for the input data register 0.44 0.52 ns t ihe enable hold time for the input data register 0.00 0.00 ns t iclr2q asynchronous clear-to-q of the input data register 0.54 0.64 ns t ipre2q asynchronous preset-to-q of the input data register 0.54 0.64 ns t iremclr asynchronous clear removal time fo r the input data register 0.00 0.00 ns t irecclr asynchronous clear recovery time fo r the input data register 0.27 0.31 ns t irempre asynchronous preset removal time fo r the input data register 0.00 0.00 ns t irecpre asynchronous preset recovery time for the input data register 0.27 0.31 ns t iwclr asynchronous clear minimum pulse width for the input data register 0.25 0.30 ns t iwpre asynchronous preset minimum pulse width for the input data register 0.25 0.30 ns t ickmpwh clock minimum pulse width high for the input data register 0.41 0.48 ns t ickmpwl clock minimum pulse width low for the input data register 0.37 0.43 ns note: for specific junction temperature and voltage supply levels, refer to table 2-5 on page 2-5 for derating values.
automotive proasic3 flash family fpgas revision 1 2-59 output register timing characteristics figure 2-18 ? output register timing diagram preset clear dout clk data_out enable t osue 50% 50% t osud t ohd 50% 50% t oclkq 1 0 t ohe t orecpre t orempre t orecclr t oremclr t owclr t owpre t opre2q t oclr2q t ockmpwh t ockmpwl 50% 50% 50% 50% 50% 50% 50% 50% 50% 50% 50% 50% 50% 50% 50% table 2-94 ? output data register propagation delays automotive-case conditions: t j = 135c, worst-case vcc = 1.425 v parameter description ?1 std. units t oclkq clock-to-q of the output data register 0.72 0.84 ns t osud data setup time for the output data register 0.38 0.45 ns t ohd data hold time for the output data register 0.00 0.00 ns t osue enable setup time for the output data register 0.53 0.63 ns t ohe enable hold time for the output data register 0.00 0.00 ns t oclr2q asynchronous clear-to-q of the ou tput data register 0.98 1.15 ns t opre2q asynchronous preset-to-q of the output data register 0.98 1.15 ns t oremclr asynchronous clear removal time for the output data register 0.00 0.00 ns t orecclr asynchronous clear recovery time for the output data register 0.27 0.32 ns t orempre asynchronous preset removal time for the output data register 0.00 0.00 ns t orecpre asynchronous preset recovery time fo r the output data register 0.27 0.32 ns t owclr asynchronous clear minimum pulse width for the output data register 0.25 0.30 ns t owpre asynchronous preset minimum pulse width for the output data register 0.25 0.30 ns t ockmpwh clock minimum pulse width high for t he output data register 0.41 0.48 ns t ockmpwl clock minimum pulse width low for the output data register 0.37 0.43 ns note: for specific junction temperature and voltage supply levels, refer to table 2-5 on page 2-5 for derating values.
automotive proasic3 dc and switching characteristics 2-60 revision 1 table 2-95 ? output data register propagation delays automotive-case conditions: t j = 115c, worst-case vcc = 1.425 v parameter description ?1 std. units t oclkq clock-to-q of the output data register 0.70 0.82 ns t osud data setup time for the output data register 0.37 0.44 ns t ohd data hold time for the output data register 0.00 0.00 ns t osue enable setup time for the output data register 0.52 0.61 ns t ohe enable hold time for the output data register 0.00 0.00 ns t oclr2q asynchronous clear-to-q of the ou tput data register 0.96 1.12 ns t opre2q asynchronous preset-to-q of the output data register 0.96 1.12 ns t oremclr asynchronous clear removal time for the output data register 0.00 0.00 ns t orecclr asynchronous clear recovery time for the output data register 0.27 0.31 ns t orempre asynchronous preset removal time for the output data register 0.00 0.00 ns t orecpre asynchronous preset recovery time fo r the output data register 0.27 0.31 ns t owclr asynchronous clear minimum pulse width for the output data register 0.25 0.30 ns t owpre asynchronous preset minimum pulse width for the output data register 0.25 0.30 ns t ockmpwh clock minimum pulse width high for t he output data register 0.41 0.48 ns t ockmpwl clock minimum pulse width low for the output data register 0.37 0.43 ns note: for specific junction temperature and voltage supply levels, refer to table 2-5 on page 2-5 for derating values.
automotive proasic3 flash family fpgas revision 1 2-61 output enable register timing characteristics figure 2-19 ? output enable register timing diagram 50% preset clear eout clk d_enable enable t oesue 50% 50% t oesud t oehd 50% 50% t oeclkq 1 0 t oehe t oerecpre t oerempre t oerecclr t oeremclr t oewclr t oewpre t oepre2q t oeclr2q t oeckmpwh t oeckmpwl 50% 50% 50% 50% 50% 50% 50% 50% 50% 50% 50% 50% 50% 50% table 2-96 ? output enable register propagation delays automotive-case conditions: t j = 135c, worst-case vcc = 1.425 v parameter description ?1 std. units t oeclkq clock-to-q of the output enable register 0.54 0.64 ns t oesud data setup time for the output enable register 0.38 0.45 ns t oehd data hold time for the output enable register 0.00 0.00 ns t oesue enable setup time for the output enable register 0.53 0.62 ns t oehe enable hold time for the ou tput enable register 0.00 0.00 ns t oeclr2q asynchronous clear-to-q of the ou tput enable register 0.81 0.95 ns t oepre2q asynchronous preset-to-q of the output enable register 0.81 0.95 ns t oeremclr asynchronous clear removal time for the output enable register 0.00 0.00 ns t oerecclr asynchronous clear recovery time for the output enable register 0.27 0.32 ns t oerempre asynchronous preset removal time for the output enable register 0.00 0.00 ns t oerecpre asynchronous preset recovery time fo r the output enable register 0.27 0.32 ns t oewclr asynchronous clear minimum pulse width for the output enable register 0.25 0.30 ns t oewpre asynchronous preset minimum pulse width fo r the output enable register 0.25 0.30 ns t oeckmpwh clock minimum pulse width high for t he output enable register 0.41 0.48 ns t oeckmpwl clock minimum pulse width low for the output enable register 0.37 0.43 ns note: for specific junction temperature and voltage supply levels, refer to table 2-5 on page 2-5 for derating values.
automotive proasic3 dc and switching characteristics 2-62 revision 1 table 2-97 ? output enable register propagation delays automotive-case conditions: t j = 115c, worst-case vcc = 1.425 v parameter description ?1 std. units t oeclkq clock-to-q of the output enable register 0.53 0.62 ns t oesud data setup time for the output enable register 0.37 0.44 ns t oehd data hold time for the output enable register 0.00 0.00 ns t oesue enable setup time for the output enable register 0.52 0.61 ns t oehe enable hold time for the ou tput enable register 0.00 0.00 ns t oeclr2q asynchronous clear-to-q of the ou tput enable register 0.79 0.93 ns t oepre2q asynchronous preset-to-q of the output enable register 0.79 0.93 ns t oeremclr asynchronous clear removal time for the output enable register 0.00 0.00 ns t oerecclr asynchronous clear recovery time for the output enable register 0.27 0.31 ns t oerempre asynchronous preset removal time for the output enable register 0.00 0.00 ns t oerecpre asynchronous preset recovery time fo r the output enable register 0.27 0.31 ns t oewclr asynchronous clear minimum pulse width for the output enable register 0.25 0.30 ns t oewpre asynchronous preset minimum pulse width fo r the output enable register 0.25 0.30 ns t oeckmpwh clock minimum pulse width high for t he output enable register 0.41 0.48 ns t oeckmpwl clock minimum pulse width low for the output enable register 0.37 0.43 ns note: for specific junction temperature and voltage supply levels, refer to table 2-5 on page 2-5 for derating values.
automotive proasic3 flash family fpgas revision 1 2-63 ddr module specifications input ddr module figure 2-20 ? input ddr timing model table 2-98 ? parameter definitions parameter name parameter definition measuring nodes (from, to) t ddriclkq1 clock-to-out out_qr b, d t ddriclkq2 clock-to-out out_qf b, e t ddrisud data setup time of ddr input a, b t ddrihd data hold time of ddr input a, b t ddriclr2q1 clear-to-out out_qr c, d t ddriclr2q2 clear-to-out out_qf c, e t ddriremclr clear removal c, b t ddrirecclr clear recovery c, b input ddr data clk clkbuf inbuf out_qf (to core) ff2 ff1 inbuf clr ddr_in e a b c d out_qr (to core)
automotive proasic3 dc and switching characteristics 2-64 revision 1 timing characteristics figure 2-21 ? input ddr timing diagram t ddriclr2q2 t ddriremclr t ddrirecclr t ddriclr2q1 12 3 4 5 6 7 8 9 clk data clr out_qr out_qf t ddriclkq1 2 4 6 3 5 7 t ddrihd t ddrisud t ddriclkq2 table 2-99 ? input ddr propagation delays automotive-case conditions: tj = 135c, worst-case vcc = 1.425 v parameter description ?1 std. units t ddriclkq1 clock-to-out out_qr for input ddr 0.33 0.39 ns t ddriclkq2 clock-to-out out_qf for input ddr 0.47 0.56 ns t ddrisud data setup for input ddr 0.34 0.40 ns t ddrihd data hold for input ddr 0.00 0.00 ns t ddriclr2q1 asynchronous clear-to-out out_qr for input ddr 0.56 0.66 ns t ddriclr2q2 asynchronous clear-to-out out_qf for input ddr 0.69 0.82 ns t ddriremclr asynchronous clear removal time for input ddr 0.00 0.00 ns t ddrirecclr asynchronous clear recovery time for input ddr 0.27 0.32 ns t ddriwclr asynchronous clear minimum puls e width for input ddr 0.25 0.30 ns t ddrickmpwh clock minimum pulse width high for input ddr 0.41 0.48 ns t ddrickmpwl clock minimum pulse width low for input ddr 0.37 0.43 ns f ddrimax maximum frequency for input ddr tbd tbd mhz note: for specific junction temperature and voltage supply levels, refer to table 2-5 on page 2-5 for derating values.
automotive proasic3 flash family fpgas revision 1 2-65 table 2-100 ? input ddr propagation delays automotive-case conditions: t j = 115c, worst-case vcc = 1.425 v parameter description ?1 std. units t ddriclkq1 clock-to-out out_qr for input ddr 0.33 0.38 ns t ddriclkq2 clock-to-out out_qf for input ddr 0.46 0.54 ns t ddrisud data setup for input ddr 0.34 0.40 ns t ddrihd data hold for input ddr 0.00 0.00 ns t ddriclr2q1 asynchronous clear-to-out out_qr for input ddr 0.55 0.65 ns t ddriclr2q2 asynchronous clear-to-out out_qf for input ddr 0.68 0.80 ns t ddriremclr asynchronous clear removal time for input ddr 0.00 0.00 ns t ddrirecclr asynchronous clear recovery time for input ddr 0.27 0.31 ns t ddriwclr asynchronous clear minimum pulse width for input ddr 0.25 0.30 ns t ddrickmpwh clock minimum pulse width high for input ddr 0.41 0.48 ns t ddrickmpwl clock minimum pulse width low for input ddr 0.37 0.43 ns f ddrimax maximum frequency for input ddr tbd tbd mhz note: for specific junction temperature and voltage supply levels, refer to table 2-5 on page 2-5 for derating values.
automotive proasic3 dc and switching characteristics 2-66 revision 1 output ddr module figure 2-22 ? output ddr timing model table 2-101 ? parameter definitions parameter name parameter defini tion measuring nodes (from, to) t ddroclkq clock-to-out b, e t ddroclr2q asynchronous clear-to-out c, e t ddroremclr clear removal c, b t ddrorecclr clear recovery c, b t ddrosud1 data setup data_f a, b t ddrosud2 data setup data_r d, b t ddrohd1 data hold data_f a, b t ddrohd2 data hold data_r d, b data_f (from core) clk clkbuf out ff2 inbuf clr ddr_out output ddr ff1 0 1 x x x x x x x a b d e c c b outbuf data_r (from core)
automotive proasic3 flash family fpgas revision 1 2-67 timing characteristics figure 2-23 ? output ddr timing diagram 11 6 1 7 2 8 3 910 45 28 3 9 t ddroremclr t ddrohd1 t ddroremclr t ddrohd2 t ddrosud2 t ddroclkq t ddrorecclr clk data_r data_f clr out t ddroclr2q 710 4 table 2-102 ? output ddr propagation delays commercial-case conditions: t j = 135c, worst-case vcc = 1.425 v parameter description ?1 std. units t ddroclkq clock-to-out of ddr for output ddr 0.85 1.00 ns t ddrosud1 data_f data setup for output ddr 0.46 0.54 ns t ddrosud2 data_r data setup for output ddr 0.46 0.54 ns t ddrohd1 data_f data hold for output ddr 0.00 0.00 ns t ddrohd2 data_r data hold for output ddr 0.00 0.00 ns t ddroclr2q asynchronous clear-to-out for output ddr 0.97 1.15 ns t ddroremclr asynchronous clear removal time for output ddr 0.00 0.00 ns t ddrorecclr asynchronous clear recovery time for output ddr 0.27 0.32 ns t ddrowclr1 asynchronous clear minimum pulse width for output ddr 0.25 0.30 ns t ddrockmpwh clock minimum pulse width high for the output ddr 0.41 0.48 ns t ddrockmpwl clock minimum pulse width low for the output ddr 0.37 0.43 ns f ddomax maximum frequency for the output ddr tbd tbd mhz note: for specific junction temperature and voltage supply levels, refer to table 2-5 on page 2-5 for derating values.
automotive proasic3 dc and switching characteristics 2-68 revision 1 table 2-103 ? output ddr propagation delays commercial-case conditions: t j = 115c, worst-case vcc = 1.425 v parameter description ?1 std. units t ddroclkq clock-to-out of ddr for output ddr 0.84 0.98 ns t ddrosud1 data_f data setup for output ddr 0.45 0.53 ns t ddrosud2 data_r data setup for output ddr 0.45 0.53 ns t ddrohd1 data_f data hold for output ddr 0.00 0.00 ns t ddrohd2 data_r data hold for output ddr 0.00 0.00 ns t ddroclr2q asynchronous clear-to-out for output ddr 0.96 1.12 ns t ddroremclr asynchronous clear removal time for output ddr 0.00 0.00 ns t ddrorecclr asynchronous clear recovery time for output ddr 0.27 0.31 ns t ddrowclr1 asynchronous clear minimum pulse width for output ddr 0.25 0.30 ns t ddrockmpwh clock minimum pulse width high for the output ddr 0.41 0.48 ns t ddrockmpwl clock minimum pulse width low for the output ddr 0.37 0.43 ns f ddomax maximum frequency for the output ddr tbd tbd mhz note: for specific junction temperature and voltage supply levels, refer to table 2-5 on page 2-5 for derating values.
automotive proasic3 flash family fpgas revision 1 2-69 versatile characteristics versatile specifications as a combinatorial module the proasic3 library offers all combinations of lut- 3 combinatorial functions. in this section, timing characteristics are presented for a sample of the library. for more details, refer to the fusion, igloo/e, and proasic3/e macro library guide . figure 2-24 ? sample of combinatorial cells maj3 a c by mux2 b 0 1 a s y ay b b a xor2 y nor2 b a y b a y or2 inv a y and2 b a y nand3 b a c xor3 y b a c nand2
automotive proasic3 dc and switching characteristics 2-70 revision 1 figure 2-25 ? timing model and waveforms t pd a b t pd = max(t pd(rr) , t pd(rf) , t pd(ff) , t pd(fr) ) where edges are applicable for the particular combinatorial cell y nand2 or any combinatorial logic t pd t pd 50% vcc vcc vcc 50% gnd a, b, c 50% 50% 50% (rr) (rf) gnd out out gnd 50% (ff) (fr) t pd t pd
automotive proasic3 flash family fpgas revision 1 2-71 timing characteristics table 2-104 ? combinatorial cell propagation delays automotive-case conditions: t j = 135c, worst-case vcc = 1.425 v combinatorial cell equation parameter ?1 std. units inv y = !a t pd 0.49 0.57 ns and2 y = a b t pd 0.57 0.67 ns nand2 y = !(a b) t pd 0.57 0.67 ns or2 y = a + b t pd 0.59 0.69 ns nor2 y = !(a + b) t pd 0.59 0.69 ns xor2 y = a bt pd 0.90 1.05 ns maj3 y = maj(a , b, c) t pd 0.85 1.00 ns xor3 y = a b ct pd 1.06 1.25 ns mux2 y = a !s + b s t pd 0.62 0.72 ns and3 y = a b c t pd 0.68 0.80 ns note: for specific junction temperature and voltage supply levels, refer to table 2-5 on page 2-5 for derating values. table 2-105 ? combinatorial cell propagation delays automotive-case conditions: t j = 115c, worst-case vcc = 1.425 v combinatorial cell equation parameter ?1 std. units inv y = !a t pd 0.48 0.56 ns and2 y = a b t pd 0.56 0.66 ns nand2 y = !(a b) t pd 0.56 0.66 ns or2 y = a + b t pd 0.58 0.68 ns nor2 y = !(a + b) t pd 0.58 0.68 ns xor2 y = a bt pd 0.88 1.03 ns maj3 y = maj(a , b, c) t pd 0.83 0.98 ns xor3 y = a b ct pd 1.04 1.23 ns mux2 y = a !s + b s t pd 0.60 0.71 ns and3 y = a b c t pd 0.67 0.79 ns note: for specific junction temperature and voltage supply levels, refer to table 2-5 on page 2-5 for derating values.
automotive proasic3 dc and switching characteristics 2-72 revision 1 versatile specifications as a sequential module the proasic3 library offers a wide variety of sequentia l cells, including flip-flops and latches. each has a data input and optional enable, clear, or preset. in this section, timing characteristics are presented for a representative sample from the libra ry. for more details, refer to the fusion, igloo/e and proasic3/e macro library guide . figure 2-26 ? sample of sequential cells dq dfn1 data clk out d q dfn1c1 data clk out clr dq dfi1e1p1 data clk out en pre d q dfn1e1 data clk out en
automotive proasic3 flash family fpgas revision 1 2-73 timing characteristics figure 2-27 ? timing model and waveforms pre clr out clk data en t sue 50% 50% t sud t hd 50% 50% t clkq 0 t he t recpre t rempre t recclr t remclr t wclr t wpre t pre2q t clr2q t ckmpwh t ckmpwl 50% 50% 50% 50% 50% 50% 50% 50% 50% 50% 50% 50% 50% 50% 50% table 2-106 ? register delays automotive-case conditions: t j = 135c, worst-case vcc = 1.425 v parameter description ?1 std. units t clkq clock-to-q of the co re register 0.67 0.79 ns t sud data setup time for the core register 0.52 0.61 ns t hd data hold time for the core register 0.00 0.00 ns t sue enable setup time for the core register 0.55 0.65 ns t he enable hold time for the core register 0.00 0.00 ns t clr2q asynchronous clear-to-q of t he core register 0.49 0.57 ns t pre2q asynchronous preset-to-q of the core register 0.49 0.57 ns t remclr asynchronous clear removal time for the core register 0.00 0.00 ns t recclr asynchronous clear recovery time for the core register 0.27 0.32 ns t rempre asynchronous preset removal time for the core register 0.00 0.00 ns t recpre asynchronous preset recovery time for the core register 0.27 0.32 ns t wclr asynchronous clear minimum pulse width for the core register 0.25 0.30 ns t wpre asynchronous preset minimum pulse wi dth for the core register 0.25 0.30 ns t ckmpwh clock minimum pulse width high for the core register 0.41 0.48 ns t ckmpwl clock minimum pulse width low for the core register 0.37 0.43 ns note: for specific junction temperature and voltage supply levels, refer to table 2-5 on page 2-5 for derating values.
automotive proasic3 dc and switching characteristics 2-74 revision 1 table 2-107 ? register delays automotive-case conditions: t j = 115c, worst-case vcc = 1.425 v parameter description ?1 std. units t clkq clock-to-q of the co re register 0.66 0.77 ns t sud data setup time for the core register 0.51 0.60 ns t hd data hold time for the core register 0.00 0.00 ns t sue enable setup time for the core register 0.54 0.64 ns t he enable hold time for the core register 0.00 0.00 ns t clr2q asynchronous clear-to-q of t he core register 0.48 0.56 ns t pre2q asynchronous preset-to-q of the core register 0.48 0.56 ns t remclr asynchronous clear removal time for the core register 0.00 0.00 ns t recclr asynchronous clear recovery time for the core register 0.27 0.31 ns t rempre asynchronous preset removal time for the core register 0.00 0.00 ns t recpre asynchronous preset recovery time for the core register 0.27 0.31 ns t wclr asynchronous clear minimum pulse width for the core register 0.25 0.30 ns t wpre asynchronous preset minimum pulse wi dth for the core register 0.25 0.30 ns t ckmpwh clock minimum pulse width high for the core register 0.41 0.48 ns t ckmpwl clock minimum pulse width low for the core register 0.37 0.43 ns note: for specific junction temperature and voltage supply levels, refer to table 2-5 on page 2-5 for derating values.
automotive proasic3 flash family fpgas revision 1 2-75 global resource characteristics a3p250 clock tree topology clock delays are device-specific. figure 2-28 is an example of a global tree used for clock routing. the global tree presented in figure 2-28 is driven by a ccc located on the west side of the a3p250 device. it is used to drive all d-flip-flops in the device. figure 2-28 ? example of global tree use in an a3p250 device for clock routing central global rib versatile rows global spine ccc
automotive proasic3 dc and switching characteristics 2-76 revision 1 global tree timing characteristics global clock delays include the central rib delay, the spine delay, and the row delay. delays do not include i/o input buffer clock delays, as these are i/o standard?dependent, and the clock may be driven and conditioned internally by the ccc module. for more details on clock conditioning capabilities, refer to the "clock conditioning circuits" section on page 2-80 . table 2-114 on page 2-79 to table 2-125 on page 2-98 present minimum and maximum global clock delays within each device. minimum and maximum delays are measured with minimum and maximum loading. timing characteristics table 2-108 ? a3p060 global resource commercial-case conditions: t j = 135c, vcc = 1.425 v parameter description ?1 std. units min. 1 max. 2 min. 1 max. 2 t rckl input low delay for global clock 0.87 1.16 1.02 1.37 ns t rckh input high delay for global clock 0.86 1.20 1.01 1.42 ns t rckmpwh minimum pulse width high for global clock ns t rckmpwl minimum pulse width low for global clock ns t rcksw maximum skew for global clock 0.35 0.41 ns f rmax maximum frequency for global clock mhz notes: 1. value reflects minimum load. the delay is measured from the ccc output to the clock pin of a sequential element, located in a lightly loaded row (single element is connected to the global net). 2. value reflects maximum load. the delay is measured on the clock pin of the farthest sequential element, located in a fully loaded row (all available flip-flops are connected to the global net in the row). 3. for specific junction temperature and voltage supply levels, refer to table 2-5 on page 2-5 for derating values. table 2-109 ? a3p060 global resource commercial-case conditions: t j = 115c, v cc = 1.425 v parameter description ?1 std. units min. 1 max. 2 min. 1 max. 2 t rckl input low delay for global clock 0.85 1.13 1.00 1.33 ns t rckh input high delay for global clock 0.84 1.18 0.99 1.38 ns t rckmpwh minimum pulse width high for global clock ns t rckmpwl minimum pulse width low for global clock ns t rcksw maximum skew for global clock 0.34 0.40 ns f rmax maximum frequency for global clock mhz notes: 1. value reflects minimum load. the delay is measured from the ccc output to the clock pin of a sequential element, located in a lightly loaded row (single element is connected to the global net). 2. value reflects maximum load. the delay is measured on the clock pin of the farthest sequential element, located in a fully loaded row (all available flip-flops are connected to the global net in the row). 3. for specific junction temperature and voltage supply levels, refer to table 2-5 on page 2-5 for derating values.
automotive proasic3 flash family fpgas revision 1 2-77 table 2-110 ? a3p125 global resource commercial-case conditions: t j = 135c, vcc = 1.425 v parameter description ?1 std. units min. 1 max. 2 min. 1 max. 2 t rckl input low delay for global clock 0.93 1.22 1.09 1.43 ns t rckh input high delay for global clock 0.92 1.26 1.08 1.49 ns t rckmpwh minimum pulse width high for global clock ns t rckmpwl minimum pulse width low for global clock ns t rcksw maximum skew for global clock 0.35 0.41 ns f rmax maximum frequency for global clock mhz notes: 1. value reflects minimum load. the delay is measured from the ccc output to the clock pin of a sequential element, located in a lightly loaded row (single element is connected to the global net). 2. value reflects maximum load. the delay is measured on the clock pin of the farthest sequential element, located in a fully loaded row (all available flip-flops are connected to the global net in the row). 3. for specific junction temperature and voltage supply levels, refer to table 2-5 on page 2-5 for derating values. table 2-111 ? a3p125 global resource commercial-case conditions: t j = 115c, vcc = 1.425 v parameter description ?1 std. units min. 1 max. 2 min. 1 max. 2 t rckl input low delay for global clock 0.90 1.19 1.06 1.40 ns t rckh input high delay for global clock 0.90 1.23 1.05 1.45 ns t rckmpwh minimum pulse width high for global clock ns t rckmpwl minimum pulse width low for global clock ns t rcksw maximum skew for global clock 0.34 0.40 ns f rmax maximum frequency for global clock mhz notes: 1. value reflects minimum load. the delay is measured from the ccc output to the clock pin of a sequential element, located in a lightly loaded row (single element is connected to the global net). 2. value reflects maximum load. the delay is measured on the clock pin of the farthest sequential element, located in a fully loaded row (all available flip-flops are connected to the global net in the row). 3. for specific junction temperature and voltage supply levels, refer to table 2-5 on page 2-5 for derating values.
automotive proasic3 dc and switching characteristics 2-78 revision 1 table 2-112 ? a3p250 global resource commercial-case conditions: t j = 135c, vcc = 1.425 v parameter description ?1 std. units min. 1 max. 2 min. 1 max. 2 t rckl input low delay for global clock 0.96 1.25 1.13 1.47 ns t rckh input high delay for global clock 0.94 1.28 1.10 1.51 ns t rckmpwh minimum pulse width high for global clock ns t rckmpwl minimum pulse width low for global clock ns t rcksw maximum skew for global clock 0.35 0.41 ns f rmax maximum frequency for global clock mhz notes: 1. value reflects minimum load. the delay is measured from the ccc output to the clock pin of a sequential element, located in a lightly loaded row (single element is connected to the global net). 2. value reflects maximum load. the delay is measured on the clock pin of the farthest sequential element, located in a fully loaded row (all available flip-flops are connected to the global net in the row). 3. for specific junction temperature and voltage supply levels, refer to table 2-5 on page 2-5 for derating values. table 2-113 ? a3p250 global resource commercial-case conditions: t j = 115c, vcc = 1.425 v parameter description ?1 std. units min. 1 max. 2 min. 1 max. 2 t rckl input low delay for global clock 0.94 1.22 1.10 1.44 ns t rckh input high delay for global clock 0.92 1.25 1.08 1.47 ns t rckmpwh minimum pulse width high for global clock ns t rckmpwl minimum pulse width low for global clock ns t rcksw maximum skew for global clock 0.34 0.40 ns f rmax maximum frequency for global clock mhz notes: 1. value reflects minimum load. the delay is measured from the ccc output to the clock pin of a sequential element, located in a lightly loaded row (single element is connected to the global net). 2. value reflects maximum load. the delay is measured on the clock pin of the farthest sequential element, located in a fully loaded row (all available flip-flops are connected to the global net in the row). 3. for specific junction temperature and voltage supply levels, refer to table 2-5 on page 2-5 for derating values.
automotive proasic3 flash family fpgas revision 1 2-79 table 2-114 ? a3p1000 global resource automotive-case conditions: t j = 135c, vcc = 1.425 v parameter description ?1 std. units min. 1 max. 2 min. 1 max. 2 t rckl input low delay for global clock 1.17 1.46 1.37 1.72 ns t rckh input high delay for global clock 1.15 1.50 1.36 1.76 ns t rckmpwh minimum pulse width high for global clock ns t rckmpwl minimum pulse width low for global clock ns t rcksw maximum skew for global clock 0.35 0.41 ns f rmax maximum frequency for global clock mhz notes: 1. value reflects minimum load. the delay is measured from the ccc output to the clock pin of a sequential element, located in a lightly loaded row (single element is connected to the global net). 2. value reflects maximum load. the delay is measured on the clock pin of the farthest sequential element, located in a fully loaded row (all available flip-flops are connected to the global net in the row). 3. for specific junction temperature and voltage supply levels, refer to table 2-5 on page 2-5 for derating values. table 2-115 ? a3p1000 global resource automotive-case conditions: t j = 115c, vcc = 1.425 v parameter description ?1 std. units min. 1 max. 2 min. 1 max. 2 t rckl input low delay for global clock 1.14 1.43 1.34 1.68 ns t rckh input high delay for global clock 1.13 1.46 1.32 1.72 ns t rckmpwh minimum pulse width high for global clock ns t rckmpwl minimum pulse width low for global clock ns t rcksw maximum skew for global clock 0.34 0.40 ns f rmax maximum frequency for global clock mhz notes: 1. value reflects minimum load. the delay is measured from the ccc output to the clock pin of a sequential element, located in a lightly loaded row (single element is connected to the global net). 2. value reflects maximum load. the delay is measured on the clock pin of the farthest sequential element, located in a fully loaded row (all available flip-flops are connected to the global net in the row). 3. for specific junction temperature and voltage supply levels, refer to table 2-5 on page 2-5 for derating values.
automotive proasic3 dc and switching characteristics 2-80 revision 1 clock conditioning circuits ccc electrical specifications timing characteristics table 2-116 ? automotive proasic3 ccc/pll specification parameter minimum typical maximum units clock conditioning circuitry input frequency f in_ccc 1.5 350 mhz clock conditioning circuitry output frequency f out_ccc 0.75 350 mhz delay increments in programmable delay blocks 1, 2 160 ps number of programmable values in ea ch programmable delay block 32 input period jitter 1.5 ns ccc output peak-to-peak period jitter f ccc_out max peak-to-peak period jitter 1 global network used 3 global networks used 0.75 mhz to 24 mhz 0.50% 0.70% 24 mhz to 100 mhz 1.00% 1.20% 100 mhz to 250 mhz 1.75% 2.00% 250 mhz to 350 mhz 2.50% 5.60% acquisition time (a3p250 and a3p1000 only) lockcontrol = 0 300 s lockcontrol = 1 300 s (all other dies) lockcontrol = 0 300 s lockcontrol = 1 6.0 ms tracking jitter 4 (a3p250 and a3p1000 only) lockcontrol = 0 1.6 ns lockcontrol = 1 1.6 ns (all other dies) lockcontrol = 0 1.6 ns lockcontrol = 1 0.8 ns output duty cycle 48.5 51.5 % delay range in block: programmable delay 1 1, 2 0.6 5.56 ns delay range in block: programmable delay 2 1, 2 0.025 5.56 ns delay range in block: fixed delay 1, 2 2.2 ns notes: 1. this delay is a function of voltage and temperature. see table 2-5 on page 2-5 for deratings. 2. t j = 25c, vcc = 1.5 v 3. tracking jitter is defined as the variation in clock edge position of pll outputs with reference to the pll input clock edge. tracking jitter does not measure the variation in pll output period, which is covered by the period jitter parameter.
automotive proasic3 flash family fpgas revision 1 2-81 note: peak-to-peak jitter meas urements are defined by t peak-to-peak = t period_max ? t period_min . figure 2-29 ? peak-to-peak jitter definition t period_max t period_min output signal
automotive proasic3 dc and switching characteristics 2-82 revision 1 embedded sram and fifo characteristics sram figure 2-30 ? ram models fifo4k18 rw2 rd17 rw1 rd16 rw0 ww2 ww1 ww0 rd0 estop fstop full afull empty afval11 aempty afval10 afval0 aeval11 aeval10 aeval0 ren rblk rclk wen wblk wclk rpipe wd17 wd16 wd0 reset addra11 douta8 douta7 douta0 doutb8 doutb7 doutb0 addra10 addra0 dina8 dina7 dina0 widtha1 widtha0 pipea wmodea blka wena clka addrb11 addrb10 addrb0 dinb8 dinb7 dinb0 widthb1 widthb0 pipeb wmodeb blkb wenb clkb ram4k9 raddr8 rd17 raddr7 rd16 raddr0 rd0 wd17 wd16 wd0 ww1 ww0 rw1 rw0 pipe ren rclk ram512x18 waddr8 waddr7 waddr0 wen wclk reset reset
automotive proasic3 flash family fpgas revision 1 2-83 timing waveforms figure 2-31 ? ram read for pass-through output figure 2-32 ? ram read for pipelined output clk add blk_b wen_b do a 0 a 1 a 2 d 0 d 1 d 2 t cyc t ckh t ckl t as t ah t bks t ens t enh t doh1 t bkh d n t ckq1 clk add blk_b wen_b do a 0 a 1 a 2 d 0 d 1 t cyc t ckh t ckl t as t ah t bks t ens t enh t doh2 t ckq2 t bkh d n
automotive proasic3 dc and switching characteristics 2-84 revision 1 figure 2-33 ? ram write, output retained (wmode = 0) figure 2-34 ? ram write, output as wr ite data (wmode = 1) t cyc t ckh t ckl a 0 a 1 a 2 di 0 di 1 t as t ah t bks t ens t enh t ds t dh clk blk_b wen_b add di d n do t bkh d 2 t cyc t ckh t ckl a 0 a 1 a 2 di 0 di 1 t as t ah t bks t ens t ds t dh clk blk_b wen_b add di t bkh do (pass-through) di 1 d n di 0 do (pipelined) di 0 di 1 d n di 2
automotive proasic3 flash family fpgas revision 1 2-85 figure 2-35 ? write access after write to same address clk1 clk2 wen_b1 wen_b2 add1 add2 di1 di2 do2 (pass-through) do2 (pipelined) a 0 t ah t as t ah t as t dh t cckh t ds t ckq1 t ckq2 d 1 a 1 d 2 a 3 d 3 a 0 d 0 d n d 0 d n d 0 a 0 a 4 d 4
automotive proasic3 dc and switching characteristics 2-86 revision 1 figure 2-36 ? read access after write to same address clk1 clk2 wen_b1 wen_b2 add1 add2 di1 do2 (pass-through) do2 (pipelined) a 0 t ah t as t ah t as t dh t ds t wro t ckq1 t ckq2 d 0 a 0 a 1 a 4 d n d n d 0 d 0 d 1 a 2 d 2 a 3 d 3
automotive proasic3 flash family fpgas revision 1 2-87 figure 2-37 ? write access after read to same address figure 2-38 ? ram reset a 0 a 1 a 0 a 0 a 1 a 3 d 1 d 2 d 3 t ah t as t ah t as t ckq1 t ckq1 t ckq2 t cckh clk1 add1 wen_b1 do1 (pass-through) do1 (pipelined) clk2 add2 di2 wen_b2 d n d n d 0 d 1 d 0 clk reset_b do d n t cyc t ckh t ckl t rstbq d m
automotive proasic3 dc and switching characteristics 2-88 revision 1 timing characteristics table 2-117 ? ram4k9 automotive-case conditions: t j = 135c, worst-case vcc = 1.425 v parameter description ?1 std. units t as address setup time 0.30 0.36 ns t ah address hold time 0.00 0.00 ns t ens ren_b, wen_b setup time 0.17 0.20 ns t enh ren_b, wen_b hold time 0.12 0.14 ns t bks blk_b setup time 0.28 0.33 ns t bkh blk_b hold time 0.02 0.03 ns t ds input data (di) setup time 0.22 0.26 ns t dh input data (di) hold time 0.00 0.00 ns t ckq1 clock high to new data valid on do (output retained, wmode = 0) 2.17 2.55 ns clock high to new data valid on do (flow-through, wmode = 1) 2.86 3.37 ns t ckq2 clock high to new data valid on do (pipelined) 1.09 1.28 ns t wro address collision clk-to-clk delay for reliable read access after write on same address tbd tbd ns t cckh address collision clk-to-clk delay for re liable write access after write/read on same address tbd tbd ns t rstbq reset_b low to data out low on do (flow-through) 1.12 1.32 ns reset_b low to data out low on do (pipelined) 1.12 1.32 ns t remrstb reset_b removal 0.35 0.41 ns t recrstb reset_b recovery 1.82 2.14 ns t mpwrstb reset_b minimum pulse width 0.26 0.30 ns t cyc clock cycle time 3.93 4.62 ns f max maximum frequency 255 217 mhz note: for specific junction temperature and voltage supply levels, refer to table 2-5 on page 2-5 for derating values.
automotive proasic3 flash family fpgas revision 1 2-89 table 2-118 ? ram512x18 automotive-case conditions: t j = 135c, worst-case vcc = 1.425 v parameter description ?1 std. units t as address setup time 0.30 0.35 ns t ah address hold time 0.00 0.00 ns t ens ren_b, wen_b setup time 0.11 0.13 ns t enh ren_b, wen_b hold time 0.07 0.08 ns t ds input data (di) setup time 0.22 0.26 ns t dh input data (di) hold time 0.00 0.00 ns t ckq1 clock high to new data valid on do (output retained, wmode = 0) 2.58 3.03 ns t ckq2 clock high to new data valid on do (pipelined) 1.07 1.26 ns t wro address collision clk-to-clk delay for reliable read access after write on same address tbd tbd ns t cckh address collision clk-to-clk delay for re liable write access after write/read on same address tbd tbd ns t rstbq reset_b low to data out low on do (flow-through) 1.10 1.29 ns reset_b low to data out low on do (pipelined ) 1.10 1.29 ns t remrstb reset_b removal 0.34 0.40 ns t recrstb reset_b recovery 1.79 2.10 ns t mpwrstb reset_b minimum pulse width 0.25 0.30 ns t cyc clock cycle time 3.85 4.53 ns f max maximum frequency 260 221 mhz note: for specific junction temperature and voltage supply levels, refer to table 2-5 on page 2-5 for derating values.
automotive proasic3 dc and switching characteristics 2-90 revision 1 table 2-119 ? ram4k9 automotive-case conditions: t j = 115c, worst case vcc = 1.425 v parameter description ?1 std. units t as address setup time 0.30 0.35 ns t ah address hold time 0.00 0.00 ns t ens ren_b, wen_b setup time 0.17 0.20 ns t enh ren_b, wen_b hold time 0.12 0.14 ns t bks blk_b setup time 0.28 0.33 ns t bkh blk_b hold time 0.02 0.03 ns t ds input data (di) setup time 0.22 0.26 ns t dh input data (di) hold time 0.00 0.00 ns t ckq1 clock high to new data valid on do (output retained, wmode = 0) 2.13 2.50 ns clock high to new data valid on do (flow-through, wmode = 1) 2.81 3.30 ns t ckq2 clock high to new data valid on do (pipelined) 1.07 1.25 ns t wro address collision clk-to-clk delay for re liable read access after write on same address tbd tbd ns t cckh address collision clk-to-clk delay for reliable write access after write/read on same address tbd tbd ns t rstbq reset_b low to data out low on do (flow-thro ugh) 1.10 1.29 ns reset_b low to data out low on do (pipelin ed) 1.10 1.29 ns t remrstb reset_b removal 0.34 0.40 ns t recrstb reset_b recovery 1.79 2.10 ns t mpwrstb reset_b minimum pulse width 0.25 0.30 ns t cyc clock cycle time 3.85 4.53 ns f max maximum frequency 260 221 mhz note: for specific junction temperature and voltage-supply levels, refer to table 2-5 on page 2-5 for derating values.
automotive proasic3 flash family fpgas revision 1 2-91 table 2-120 ? ram512x18 automotive-case conditions: t j = 115c, worst-case vcc = 1.425 v parameter description ?1 std. units t as address setup time 0.30 0.35 ns t ah address hold time 0.00 0.00 ns t ens ren_b, wen_b setup time 0.11 0.13 ns t enh ren_b, wen_b hold time 0.07 0.08 ns t ds input data (di) setup time 0.22 0.26 ns t dh input data (di) hold time 0.00 0.00 ns t ckq1 clock high to new data valid on do (output retained, wmode = 0) 2.58 3.03 ns t ckq2 clock high to new data valid on do (pipelined) 1.07 1.26 ns t wro address collision clk-to-clk delay for reliable read access after write on same address tbd tbd ns t cckh address collision clk-to-clk delay for re liable write access after write/read on same address tbd tbd ns t rstbq reset_b low to data out low on do (flow-through) 1.10 1.29 ns reset_b low to data out low on do (pipelined ) 1.10 1.29 ns t remrstb reset_b removal 0.34 0.40 ns t recrstb reset_b recovery 1.79 2.10 ns t mpwrstb reset_b minimum pulse width 0.25 0.30 ns t cyc clock cycle time 3.85 4.53 ns f max maximum frequency 260 221 mhz note: for specific junction temperature and voltage supply levels, refer to table 2-5 on page 2-5 for derating values.
automotive proasic3 dc and switching characteristics 2-92 revision 1 fifo figure 2-39 ? fifo model fifo4k18 rw2 rd17 rw1 rd16 rw0 ww2 ww1 ww0 rd0 estop fstop full afull empty afval11 aempty afval10 afval0 aeval11 aeval10 aeval0 ren rblk rclk wen wblk wclk rpipe wd17 wd16 wd0 reset
automotive proasic3 flash family fpgas revision 1 2-93 timing waveforms figure 2-40 ? fifo reset figure 2-41 ? fifo empty flag and aempty flag assertion match (a 0 ) t mpwrstb t rstfg t rstck t rstaf rclk/ wclk reset_b empty aempty wa/ra (address counter) t rstfg t rstaf full afull rclk no match no match dist = aef_th match (empty) t ckaf t rckef empty aempty t cyc wa/ra (address counter)
automotive proasic3 dc and switching characteristics 2-94 revision 1 figure 2-42 ? fifo full flag and afull flag assertion figure 2-43 ? fifo empty flag and aempty flag deassertion figure 2-44 ? fifo full flag and afull flag deassertion no match no match dist = aff_th match (full) t ckaf t wckff t cyc wclk full afull wa/ra (address counter) wclk wa/ra (address counter) match (empty) no match no match no match dist = aef_th + 1 no match rclk empty 1st rising edge after 1st write 2nd rising edge after 1st write t rckef t ckaf aempty dist = aff_th ? 1 match (full) no match no match no match no match t wckf t ckaf 1st rising edge after 1st read 1st rising edge after 2nd read rclk wa/ra (address counter) wclk full afull
automotive proasic3 flash family fpgas revision 1 2-95 timing characteristics table 2-121 ? fifo worst-case automoti ve conditions: t j = 135c, vcc = 1.425 v parameter description ?1 std. units t ens ren_b, wen_b setup time 1.97 1.67 ns t enh ren_b, wen_b hold time 0.03 0.02 ns t bks blk_b setup time 0.28 0.32 ns t bkh blk_b hold time 0.00 0.00 ns t ds input data (di) setup time 0.26 0.22 ns t dh input data (di) hold time 0.00 0.00 ns t ckq1 clock high to new data valid on do (flow-through) 3.37 2.86 ns t ckq2 clock high to new data valid on do (pipelined) 1.28 1.09 ns t rckef rclk high to empty flag valid 2.45 2.09 ns t wckff wclk high to full flag valid 2.33 1.98 ns t ckaf clock high to almost empty/full flag valid 8.85 7.53 ns t rstfg reset_b low to empty/fu ll flag valid 2.42 2.06 ns t rstaf reset_b low to almost empt y/full flag valid 8.76 7.45 ns t rstbq reset_b low to data out low on do (flow-through) 1.32 1.12 ns reset_b low to data out low on do (pipelined) 1.32 1.12 ns t remrstb reset_b removal 0.41 0.35 ns t recrstb reset_b recovery 2.14 1.82 ns t mpwrstb reset_b minimum pulse width 0.30 0.26 ns t cyc clock cycle time 4.62 3.93 ns f max maximum frequency for fifo 217 255 mhz note: for specific junction temperature and voltage supply levels, refer to table 2-5 on page 2-5 for derating values.
automotive proasic3 dc and switching characteristics 2-96 revision 1 table 2-122 ? fifo worst-case automoti ve conditions: t j = 115c, vcc = 1.425 v parameter description ?1 std. units t ens ren_b, wen_b setup time 1.93 1.64 ns t enh ren_b, wen_b hold time 0.03 0.02 ns t bks blk_b setup time 0.27 0.32 ns t bkh blk_b hold time 0.00 0.00 ns t ds input data (di) setup time 0.26 0.22 ns t dh input data (di) hold time 0.00 0.00 ns t ckq1 clock high to new data valid on do (flow-through) 3.30 2.81 ns t ckq2 clock high to new data valid on do (pipelined) 1.25 1.07 ns t rckef rclk high to empty flag valid 2.41 2.05 ns t wckff wclk high to full flag valid 2.29 1.95 ns t ckaf clock high to almost empty/full flag valid 8.68 7.38 ns t rstfg reset_b low to empty/fu ll flag valid 2.37 2.02 ns t rstaf reset_b low to almost empt y/full flag valid 8.59 7.30 ns t rstbq reset_b low to data out low on do (flow-through) 1.29 1.10 ns reset_b low to data out low on do (pipelined) 1.29 1.10 ns t remrstb reset_b removal 0.40 0.34 ns t recrstb reset_b recovery 2.10 1.79 ns t mpwrstb reset_b minimum pulse width 0.30 0.25 ns t cyc clock cycle time 4.53 3.85 ns f max maximum frequency for fifo 221 260 mhz note: for specific junction temperature and voltage supply levels, refer to table 2-5 on page 2-5 for derating values.
automotive proasic3 flash family fpgas revision 1 2-97 embedded flashrom characteristics timing characteristics figure 2-45 ? timing diagram a 0 a 1 t su t hold t su t hold t su t hold t ckq2 t ckq2 t ckq2 clk a ddress data d 0 d 0 d 1 table 2-123 ? embedded flashrom access time automotive-case conditions: t j = 135c, worst-case vcc = 1.425 v parameter description ?1 std. units t su address setup time 0.65 0.76 ns t hold address hold time 0.00 0.00 ns t ck2q clock to out 19.73 23.20 ns f max maximum clock frequency 15 15 mhz table 2-124 ? embedded flashrom access time automotive-case conditions: t j = 115c, worst-case vcc = 1.425 v parameter description ?1 std. units t su address setup time 0.64 0.75 ns t hold address hold time 0.00 0.00 ns t ck2q clock to out 19.35 22.74 ns f max maximum clock frequency 15 15 mhz
automotive proasic3 dc and switching characteristics 2-98 revision 1 jtag 1532 characteristics jtag timing delays do not include jtag i/os. to obtai n complete jtag timing, add i/o buffer delays to the corresponding standard selected; refer to the i/o timing characteristics in the "user i/o characteristics" section on page 2-12 for more details. timing characteristics table 2-125 ? jtag 1532 commercial-case conditions: t j = 70c, worst-case vcc = 1.425 v parameter description ?2 ?1 std. units t disu test data input setup time ns t dihd test data input hold time ns t tmssu test mode select setup time ns t tmdhd test mode select hold time ns t tck2q clock to q (data out) ns t rstb2q reset to q (data out) ns f tckmax tck maximum frequency 20 20 20 mhz t trstrem resetb removal time ns t trstrec resetb recovery time ns t trstmpw resetb minimum pulse ns note: for specific junction temperature and voltage supply levels, refer to table 2-5 on page 2-5 for derating values.
revision 1 3-1 automotive proasic3 flash family fpgas 3 ? package pin assignments 100-pin vqfp note for package manufacturing and environmental information, visit the resource center at http://www.actel.com/products /solutions/package/docs.aspx . note: this is the top view of the package. 1 100
package pin assignments 3-2 revision 1 100-pin vqfp pin number a3p060 function 1gnd 2 gaa2/io51rsb1 3 io52rsb1 4 gab2/io53rsb1 5 io95rsb1 6 gac2/io94rsb1 7 io93rsb1 8 io92rsb1 9gnd 10 gfb1/io87rsb1 11 gfb0/io86rsb1 12 vcomplf 13 gfa0/io85rsb1 14 vccplf 15 gfa1/io84rsb1 16 gfa2/io83rsb1 17 vcc 18 vccib1 19 gec1/io77rsb1 20 geb1/io75rsb1 21 geb0/io74rsb1 22 gea1/io73rsb1 23 gea0/io72rsb1 24 vmv1 25 gndq 26 gea2/io71rsb1 27 geb2/io70rsb1 28 gec2/io69rsb1 29 io68rsb1 30 io67rsb1 31 io66rsb1 32 io65rsb1 33 io64rsb1 34 io63rsb1 35 io62rsb1 36 io61rsb1 37 vcc 38 gnd 39 vccib1 40 io60rsb1 41 io59rsb1 42 io58rsb1 43 io57rsb1 44 gdc2/io56rsb1 45 gdb2/io55rsb1 46 gda2/io54rsb1 47 tck 48 tdi 49 tms 50 vmv1 51 gnd 52 vpump 53 nc 54 tdo 55 trst 56 vjtag 57 gda1/io49rsb0 58 gdc0/io46rsb0 59 gdc1/io45rsb0 60 gcc2/io43rsb0 61 gcb2/io42rsb0 62 gca0/io40rsb0 63 gca1/io39rsb0 64 gcc0/io36rsb0 65 gcc1/io35rsb0 66 vccib0 67 gnd 68 vcc 100-pin vqfp pin number a3p060 function 69 io31rsb0 70 gbc2/io29rsb0 71 gbb2/io27rsb0 72 io26rsb0 73 gba2/io25rsb0 74 vmv0 75 gndq 76 gba1/io24rsb0 77 gba0/io23rsb0 78 gbb1/io22rsb0 79 gbb0/io21rsb0 80 gbc1/io20rsb0 81 gbc0/io19rsb0 82 io18rsb0 83 io17rsb0 84 io15rsb0 85 io13rsb0 86 io11rsb0 87 vccib0 88 gnd 89 vcc 90 io10rsb0 91 io09rsb0 92 io08rsb0 93 gac1/io07rsb0 94 gac0/io06rsb0 95 gab1/io05rsb0 96 gab0/io04rsb0 97 gaa1/io03rsb0 98 gaa0/io02rsb0 99 io01rsb0 100 io00rsb0 100-pin vqfp pin number a3p060 function
automotive proasic3 flash family fpgas revision 1 3-3 100-pin vqfp pin number a3p250 function 1gnd 2 gaa2/io118udb3 3 io118vdb3 4 gab2/io117udb3 5 io117vdb3 6 gac2/io116udb3 7 io116vdb3 8 io112psb3 9gnd 10 gfb1/io109pdb3 11 gfb0/io109ndb3 12 vcomplf 13 gfa0/io108npb3 14 vccplf 15 gfa1/io108ppb3 16 gfa2/io107psb3 17 vcc 18 vccib3 19 gfc2/io105psb3 20 gec1/io100pdb3 21 gec0/io100ndb3 22 gea1/io98pdb3 23 gea0/io98ndb3 24 vmv3 25 gndq 26 gea2/io97rsb2 27 geb2/io96rsb2 28 gec2/io95rsb2 29 io93rsb2 30 io92rsb2 31 io91rsb2 32 io90rsb2 33 io88rsb2 34 io86rsb2 35 io85rsb2 36 io84rsb2 37 vcc 38 gnd 39 vccib2 40 io77rsb2 41 io74rsb2 42 io71rsb2 43 gdc2/io63rsb2 44 gdb2/io62rsb2 45 gda2/io61rsb2 46 gndq 47 tck 48 tdi 49 tms 50 vmv2 51 gnd 52 vpump 53 nc 54 tdo 55 trst 56 vjtag 57 gda1/io60usb1 58 gdc0/io58vdb1 59 gdc1/io58udb1 60 io52ndb1 61 gcb2/io52pdb1 62 gca1/io50pdb1 63 gca0/io50ndb1 64 gcc0/io48ndb1 65 gcc1/io48pdb1 66 vccib1 67 gnd 68 vcc 100-pin vqfp pin number a3p250 function 69 io43ndb1 70 gbc2/io43pdb1 71 gbb2/io42psb1 72 io41ndb1 73 gba2/io41pdb1 74 vmv1 75 gndq 76 gba1/io40rsb0 77 gba0/io39rsb0 78 gbb1/io38rsb0 79 gbb0/io37rsb0 80 gbc1/io36rsb0 81 gbc0/io35rsb0 82 io29rsb0 83 io27rsb0 84 io25rsb0 85 io23rsb0 86 io21rsb0 87 vccib0 88 gnd 89 vcc 90 io15rsb0 91 io13rsb0 92 io11rsb0 93 gac1/io05rsb0 94 gac0/io04rsb0 95 gab1/io03rsb0 96 gab0/io02rsb0 97 gaa1/io01rsb0 98 gaa0/io00rsb0 99 gndq 100 vmv0 100-pin vqfp pin number a3p250 function
package pin assignments 3-4 revision 1 132-pin qfn note for package manufacturing and environmental information, visit the resource center at http://www.actel.com/products /solutions/package/docs.aspx . notes: 1. this is the bottom view of the package. 2. the die attach paddle center of the package is tied to ground (gnd). a37 a1 a12 a36 d4 d3 d1 d2 a25 a48 a24 a13 b34 b1 b11 b44 b22 b12 c31 c1 c10 b33 b23 c30 c21 c40 c20 c11 optional corner pad (4x) pin a1mark
automotive proasic3 flash family fpgas revision 1 3-5 132-pin qfn pin number a3p125 function a1 gab2/io69rsb1 a2 io130rsb1 a3 vccib1 a4 gfc1/io126rsb1 a5 gfb0/io123rsb1 a6 vccplf a7 gfa1/io121rsb1 a8 gfc2/io118rsb1 a9 io115rsb1 a10 vcc a11 geb1/io110rsb1 a12 gea0/io107rsb1 a13 gec2/io104rsb1 a14 io100rsb1 a15 vcc a16 io99rsb1 a17 io96rsb1 a18 io94rsb1 a19 io91rsb1 a20 io85rsb1 a21 io79rsb1 a22 vcc a23 gdb2/io71rsb1 a24 tdi a25 trst a26 gdc1/io61rsb0 a27 vcc a28 io60rsb0 a29 gcc2/io59rsb0 a30 gca2/io57rsb0 a31 gca0/io56rsb0 a32 gcb1/io53rsb0 a33 io49rsb0 a34 vcc a35 io44rsb0 a36 gba2/io41rsb0 a37 gbb1/io38rsb0 a38 gbc0/io35rsb0 a39 vccib0 a40 io28rsb0 a41 io22rsb0 a42 io18rsb0 a43 io14rsb0 a44 io11rsb0 a45 io07rsb0 a46 vcc a47 gac1/io05rsb0 a48 gab0/io02rsb0 b1 io68rsb1 b2 gac2/io131rsb1 b3 gnd b4 gfc0/io125rsb1 b5 vcomplf b6 gnd b7 gfb2/io119rsb1 b8 io116rsb1 b9 gnd b10 geb0/io109rsb1 b11 vmv1 b12 geb2/io105rsb1 b13 io101rsb1 b14 gnd b15 io98rsb1 b16 io95rsb1 b17 gnd b18 io87rsb1 b19 io81rsb1 b20 gnd b21 gndq b22 tms b23 tdo b24 gdc0/io62rsb0 132-pin qfn pin number a3p125 function b25 gnd b26 nc b27 gcb2/io58rsb0 b28 gnd b29 gcb0/io54rsb0 b30 gcc1/io51rsb0 b31 gnd b32 gbb2/io43rsb0 b33 vmv0 b34 gba0/io39rsb0 b35 gbc1/io36rsb0 b36 gnd b37 io26rsb0 b38 io21rsb0 b39 gnd b40 io13rsb0 b41 io08rsb0 b42 gnd b43 gac0/io04rsb0 b44 gndq c1 gaa2/io67rsb1 c2 io132rsb1 c3 vcc c4 gfb1/io124rsb1 c5 gfa0/io122rsb1 c6 gfa2/io120rsb1 c7 io117rsb1 c8 vccib1 c9 gea1/io108rsb1 c10 gndq c11 gea2/io106rsb1 c12 io103rsb1 c13 vccib1 c14 io97rsb1 c15 io93rsb1 c16 io89rsb1 132-pin qfn pin number a3p125 function
package pin assignments 3-6 revision 1 c17 io83rsb1 c18 vccib1 c19 tck c20 vmv1 c21 vpump c22 vjtag c23 vccib0 c24 nc c25 nc c26 gca1/io55rsb0 c27 gcc0/io52rsb0 c28 vccib0 c29 io42rsb0 c30 gndq c31 gba1/io40rsb0 c32 gbb0/io37rsb0 c33 vcc c34 io24rsb0 c35 io19rsb0 c36 io16rsb0 c37 io10rsb0 c38 vccib0 c39 gab1/io03rsb0 c40 vmv0 d1 gnd d2 gnd d3 gnd d4 gnd 132-pin qfn pin number a3p125 function
automotive proasic3 flash family fpgas revision 1 3-7 132-pin qfn pin number a3p250 function a1 gab2/io117upb3 a2 io117vpb3 a3 vccib3 a4 gfc1/io110pdb3 a5 gfb0/io109npb3 a6 vccplf a7 gfa1/io108ppb3 a8 gfc2/io105ppb3 a9 io103ndb3 a10 vcc a11 gea1/io98ppb3 a12 gea0/io98npb3 a13 gec2/io95rsb2 a14 io91rsb2 a15 vcc a16 io90rsb2 a17 io87rsb2 a18 io85rsb2 a19 io82rsb2 a20 io76rsb2 a21 io70rsb2 a22 vcc a23 gdb2/io62rsb2 a24 tdi a25 trst a26 gdc1/io58udb1 a27 vcc a28 io54ndb1 a29 io52ndb1 a30 gca2/io51ppb1 a31 gca0/io50npb1 a32 gcb1/io49pdb1 a33 io47nsb1 a34 vcc a35 io41npb1 a36 gba2/io41ppb1 a37 gbb1/io38rsb0 a38 gbc0/io35rsb0 a39 vccib0 a40 io28rsb0 a41 io22rsb0 a42 io18rsb0 a43 io14rsb0 a44 io11rsb0 a45 io07rsb0 a46 vcc a47 gac1/io05rsb0 a48 gab0/io02rsb0 b1 io118vdb3 b2 gac2/io116udb3 b3 gnd b4 gfc0/io110ndb3 b5 vcomplf b6 gnd b7 gfb2/io106psb3 b8 io103pdb3 b9 gnd b10 geb0/io99ndb3 b11 vmv3 b12 geb2/io96rsb2 b13 io92rsb2 b14 gnd b15 io89rsb2 b16 io86rsb2 b17 gnd b18 io78rsb2 b19 io72rsb2 b20 gnd b21 gndq b22 tms b23 tdo b24 gdc0/io58vdb1 132-pin qfn pin number a3p250 function b25 gnd b26 io54pdb1 b27 gcb2/io52pdb1 b28 gnd b29 gcb0/io49ndb1 b30 gcc1/io48pdb1 b31 gnd b32 gbb2/io42pdb1 b33 vmv1 b34 gba0/io39rsb0 b35 gbc1/io36rsb0 b36 gnd b37 io26rsb0 b38 io21rsb0 b39 gnd b40 io13rsb0 b41 io08rsb0 b42 gnd b43 gac0/io04rsb0 b44 gndq c1 gaa2/io118udb3 c2 io116vdb3 c3 vcc c4 gfb1/io109ppb3 c5 gfa0/io108npb3 c6 gfa2/io107psb3 c7 io105npb3 c8 vccib3 c9 geb1/io99pdb3 c10 gndq c11 gea2/io97rsb2 c12 io94rsb2 c13 vccib2 c14 io88rsb2 c15 io84rsb2 c16 io80rsb2 132-pin qfn pin number a3p250 function
package pin assignments 3-8 revision 1 c17 io74rsb2 c18 vccib2 c19 tck c20 vmv2 c21 vpump c22 vjtag c23 vccib1 c24 io53nsb1 c25 io51npb1 c26 gca1/io50ppb1 c27 gcc0/io48ndb1 c28 vccib1 c29 io42ndb1 c30 gndq c31 gba1/io40rsb0 c32 gbb0/io37rsb0 c33 vcc c34 io24rsb0 c35 io19rsb0 c36 io16rsb0 c37 io10rsb0 c38 vccib0 c39 gab1/io03rsb0 c40 vmv0 d1 gnd d2 gnd d3 gnd d4 gnd 132-pin qfn pin number a3p250 function
automotive proasic3 flash family fpgas revision 1 3-9 144-pin fbga note for package manufacturing and environmental information, visit the resource center at http://www.actel.com/products /solutions/package/docs.aspx . note: this is the bottom view of the package. 1 2 3 4 5 6 7 8 9 10 11 12 a b c d e f g h j k l m a1 ball pad corner
package pin assignments 3-10 revision 1 144-pin fbga pin number a3p060 function a1 gndq a2 vmv0 a3 gab0/io04rsb0 a4 gab1/io05rsb0 a5 io08rsb0 a6 gnd a7 io11rsb0 a8 vcc a9 io16rsb0 a10 gba0/io23rsb0 a11 gba1/io24rsb0 a12 gndq b1 gab2/io53rsb1 b2 gnd b3 gaa0/io02rsb0 b4 gaa1/io03rsb0 b5 io00rsb0 b6 io10rsb0 b7 io12rsb0 b8 io14rsb0 b9 gbb0/io21rsb0 b10 gbb1/io22rsb0 b11 gnd b12 vmv0 c1 io95rsb1 c2 gfa2/io83rsb1 c3 gac2/io94rsb1 c4 vcc c5 io01rsb0 c6 io09rsb0 c7 io13rsb0 c8 io15rsb0 c9 io17rsb0 c10 gba2/io25rsb0 c11 io26rsb0 c12 gbc2/io29rsb0 d1 io91rsb1 d2 io92rsb1 d3 io93rsb1 d4 gaa2/io51rsb1 d5 gac0/io06rsb0 d6 gac1/io07rsb0 d7 gbc0/io19rsb0 d8 gbc1/io20rsb0 d9 gbb2/io27rsb0 d10 io18rsb0 d11 io28rsb0 d12 gcb1/io37rsb0 e1 vcc e2 gfc0/io88rsb1 e3 gfc1/io89rsb1 e4 vccib1 e5 io52rsb1 e6 vccib0 e7 vccib0 e8 gcc1/io35rsb0 e9 vccib0 e10 vcc e11 gca0/io40rsb0 e12 io30rsb0 f1 gfb0/io86rsb1 f2 vcomplf f3 gfb1/io87rsb1 f4 io90rsb1 f5 gnd f6 gnd f7 gnd f8 gcc0/io36rsb0 f9 gcb0/io38rsb0 f10 gnd f11 gca1/io39rsb0 f12 gca2/io41rsb0 144-pin fbga pin number a3p060 function g1 gfa1/io84rsb1 g2 gnd g3 vccplf g4 gfa0/io85rsb1 g5 gnd g6 gnd g7 gnd g8 gdc1/io45rsb0 g9 io32rsb0 g10 gcc2/io43rsb0 g11 io31rsb0 g12 gcb2/io42rsb0 h1 vcc h2 gfb2/io82rsb1 h3 gfc2/io81rsb1 h4 gec1/io77rsb1 h5 vcc h6 io34rsb0 h7 io44rsb0 h8 gdb2/io55rsb1 h9 gdc0/io46rsb0 h10 vccib0 h11 io33rsb0 h12 vcc j1 geb1/io75rsb1 j2 io78rsb1 j3 vccib1 j4 gec0/io76rsb1 j5 io79rsb1 j6 io80rsb1 j7 vcc j8 tck j9 gda2/io54rsb1 j10 tdo j11 gda1/io49rsb0 j12 gdb1/io47rsb0 144-pin fbga pin number a3p060 function
automotive proasic3 flash family fpgas revision 1 3-11 k1 geb0/io74rsb1 k2 gea1/io73rsb1 k3 gea0/io72rsb1 k4 gea2/io71rsb1 k5 io65rsb1 k6 io64rsb1 k7 gnd k8 io57rsb1 k9 gdc2/io56rsb1 k10 gnd k11 gda0/io50rsb0 k12 gdb0/io48rsb0 l1 gnd l2 vmv1 l3 geb2/io70rsb1 l4 io67rsb1 l5 vccib1 l6 io62rsb1 l7 io59rsb1 l8 io58rsb1 l9 tms l10 vjtag l11 vmv1 l12 trst m1 gndq m2 gec2/io69rsb1 m3 io68rsb1 m4 io66rsb1 m5 io63rsb1 m6 io61rsb1 m7 io60rsb1 m8 nc m9 tdi m10 vccib1 m11 vpump m12 gndq 144-pin fbga pin number a3p060 function
package pin assignments 3-12 revision 1 144-pin fbga pin number a3p125 function a1 gndq a2 vmv0 a3 gab0/io02rsb0 a4 gab1/io03rsb0 a5 io11rsb0 a6 gnd a7 io18rsb0 a8 vcc a9 io25rsb0 a10 gba0/io39rsb0 a11 gba1/io40rsb0 a12 gndq b1 gab2/io69rsb1 b2 gnd b3 gaa0/io00rsb0 b4 gaa1/io01rsb0 b5 io08rsb0 b6 io14rsb0 b7 io19rsb0 b8 io22rsb0 b9 gbb0/io37rsb0 b10 gbb1/io38rsb0 b11 gnd b12 vmv0 c1 io132rsb1 c2 gfa2/io120rsb1 c3 gac2/io131rsb1 c4 vcc c5 io10rsb0 c6 io12rsb0 c7 io21rsb0 c8 io24rsb0 c9 io27rsb0 c10 gba2/io41rsb0 c11 io42rsb0 c12 gbc2/io45rsb0 d1 io128rsb1 d2 io129rsb1 d3 io130rsb1 d4 gaa2/io67rsb1 d5 gac0/io04rsb0 d6 gac1/io05rsb0 d7 gbc0/io35rsb0 d8 gbc1/io36rsb0 d9 gbb2/io43rsb0 d10 io28rsb0 d11 io44rsb0 d12 gcb1/io53rsb0 e1 vcc e2 gfc0/io125rsb1 e3 gfc1/io126rsb1 e4 vccib1 e5 io68rsb1 e6 vccib0 e7 vccib0 e8 gcc1/io51rsb0 e9 vccib0 e10 vcc e11 gca0/io56rsb0 e12 io46rsb0 f1 gfb0/io123rsb1 f2 vcomplf f3 gfb1/io124rsb1 f4 io127rsb1 f5 gnd f6 gnd f7 gnd f8 gcc0/io52rsb0 f9 gcb0/io54rsb0 f10 gnd f11 gca1/io55rsb0 f12 gca2/io57rsb0 144-pin fbga pin number a3p125 function g1 gfa1/io121rsb1 g2 gnd g3 vccplf g4 gfa0/io122rsb1 g5 gnd g6 gnd g7 gnd g8 gdc1/io61rsb0 g9 io48rsb0 g10 gcc2/io59rsb0 g11 io47rsb0 g12 gcb2/io58rsb0 h1 vcc h2 gfb2/io119rsb1 h3 gfc2/io118rsb1 h4 gec1/io112rsb1 h5 vcc h6 io50rsb0 h7 io60rsb0 h8 gdb2/io71rsb1 h9 gdc0/io62rsb0 h10 vccib0 h11 io49rsb0 h12 vcc j1 geb1/io110rsb1 j2 io115rsb1 j3 vccib1 j4 gec0/io111rsb1 j5 io116rsb1 j6 io117rsb1 j7 vcc j8 tck j9 gda2/io70rsb1 j10 tdo j11 gda1/io65rsb0 j12 gdb1/io63rsb0 144-pin fbga pin number a3p125 function
automotive proasic3 flash family fpgas revision 1 3-13 k1 geb0/io109rsb1 k2 gea1/io108rsb1 k3 gea0/io107rsb1 k4 gea2/io106rsb1 k5 io100rsb1 k6 io98rsb1 k7 gnd k8 io73rsb1 k9 gdc2/io72rsb1 k10 gnd k11 gda0/io66rsb0 k12 gdb0/io64rsb0 l1 gnd l2 vmv1 l3 geb2/io105rsb1 l4 io102rsb1 l5 vccib1 l6 io95rsb1 l7 io85rsb1 l8 io74rsb1 l9 tms l10 vjtag l11 vmv1 l12 trst m1 gndq m2 gec2/io104rsb1 m3 io103rsb1 m4 io101rsb1 m5 io97rsb1 m6 io94rsb1 m7 io86rsb1 m8 io75rsb1 m9 tdi m10 vccib1 m11 vpump m12 gndq 144-pin fbga pin number a3p125 function
package pin assignments 3-14 revision 1 144-pin fbga pin number a3p250 function a1 gndq a2 vmv0 a3 gab0/io02rsb0 a4 gab1/io03rsb0 a5 io16rsb0 a6 gnd a7 io29rsb0 a8 vcc a9 io33rsb0 a10 gba0/io39rsb0 a11 gba1/io40rsb0 a12 gndq b1 gab2/io117udb3 b2 gnd b3 gaa0/io00rsb0 b4 gaa1/io01rsb0 b5 io14rsb0 b6 io19rsb0 b7 io22rsb0 b8 io30rsb0 b9 gbb0/io37rsb0 b10 gbb1/io38rsb0 b11 gnd b12 vmv1 c1 io117vdb3 c2 gfa2/io107ppb3 c3 gac2/io116udb3 c4 vcc c5 io12rsb0 c6 io17rsb0 c7 io24rsb0 c8 io31rsb0 c9 io34rsb0 c10 gba2/io41pdb1 c11 io41ndb1 c12 gbc2/io43ppb1 d1 io112ndb3 d2 io112pdb3 d3 io116vdb3 d4 gaa2/io118upb3 d5 gac0/io04rsb0 d6 gac1/io05rsb0 d7 gbc0/io35rsb0 d8 gbc1/io36rsb0 d9 gbb2/io42pdb1 d10 io42ndb1 d11 io43npb1 d12 gcb1/io49ppb1 e1 vcc e2 gfc0/io110ndb3 e3 gfc1/io110pdb3 e4 vccib3 e5 io118vpb3 e6 vccib0 e7 vccib0 e8 gcc1/io48pdb1 e9 vccib1 e10 vcc e11 gca0/io50ndb1 e12 io51ndb1 f1 gfb0/io109npb3 f2 vcomplf f3 gfb1/io109ppb3 f4 io107npb3 f5 gnd f6 gnd f7 gnd f8 gcc0/io48ndb1 f9 gcb0/io49npb1 f10 gnd f11 gca1/io50pdb1 f12 gca2/io51pdb1 144-pin fbga pin number a3p250 function g1 gfa1/io108ppb3 g2 gnd g3 vccplf g4 gfa0/io108npb3 g5 gnd g6 gnd g7 gnd g8 gdc1/io58upb1 g9 io53ndb1 g10 gcc2/io53pdb1 g11 io52ndb1 g12 gcb2/io52pdb1 h1 vcc h2 gfb2/io106pdb3 h3 gfc2/io105psb3 h4 gec1/io100pdb3 h5 vcc h6 io79rsb2 h7 io65rsb2 h8 gdb2/io62rsb2 h9 gdc0/io58vpb1 h10 vccib1 h11 io54psb1 h12 vcc j1 geb1/io99pdb3 j2 io106ndb3 j3 vccib3 j4 gec0/io100ndb3 j5 io88rsb2 j6 io81rsb2 j7 vcc j8 tck j9 gda2/io61rsb2 j10 tdo j11 gda1/io60udb1 j12 gdb1/io59udb1 144-pin fbga pin number a3p250 function
automotive proasic3 flash family fpgas revision 1 3-15 k1 geb0/io99ndb3 k2 gea1/io98pdb3 k3 gea0/io98ndb3 k4 gea2/io97rsb2 k5 io90rsb2 k6 io84rsb2 k7 gnd k8 io66rsb2 k9 gdc2/io63rsb2 k10 gnd k11 gda0/io60vdb1 k12 gdb0/io59vdb1 l1 gnd l2 vmv3 l3 geb2/io96rsb2 l4 io91rsb2 l5 vccib2 l6 io82rsb2 l7 io80rsb2 l8 io72rsb2 l9 tms l10 vjtag l11 vmv2 l12 trst m1 gndq m2 gec2/io95rsb2 m3 io92rsb2 m4 io89rsb2 m5 io87rsb2 m6 io85rsb2 m7 io78rsb2 m8 io76rsb2 m9 tdi m10 vccib2 m11 vpump m12 gndq 144-pin fbga pin number a3p250 function
package pin assignments 3-16 revision 1 144-pin fbga pin number a3p1000 function a1 gndq a2 vmv0 a3 gab0/io02rsb0 a4 gab1/io03rsb0 a5 io10rsb0 a6 gnd a7 io44rsb0 a8 vcc a9 io69rsb0 a10 gba0/io76rsb0 a11 gba1/io77rsb0 a12 gndq b1 gab2/io224pdb3 b2 gnd b3 gaa0/io00rsb0 b4 gaa1/io01rsb0 b5 io13rsb0 b6 io26rsb0 b7 io35rsb0 b8 io60rsb0 b9 gbb0/io74rsb0 b10 gbb1/io75rsb0 b11 gnd b12 vmv1 c1 io224ndb3 c2 gfa2/io206ppb3 c3 gac2/io223pdb3 c4 vcc c5 io16rsb0 c6 io29rsb0 c7 io32rsb0 c8 io63rsb0 c9 io66rsb0 c10 gba2/io78pdb1 c11 io78ndb1 c12 gbc2/io80ppb1 d1 io213pdb3 d2 io213ndb3 d3 io223ndb3 d4 gaa2/io225ppb3 d5 gac0/io04rsb0 d6 gac1/io05rsb0 d7 gbc0/io72rsb0 d8 gbc1/io73rsb0 d9 gbb2/io79pdb1 d10 io79ndb1 d11 io80npb1 d12 gcb1/io92ppb1 e1 vcc e2 gfc0/io209ndb3 e3 gfc1/io209pdb3 e4 vccib3 e5 io225npb3 e6 vccib0 e7 vccib0 e8 gcc1/io91pdb1 e9 vccib1 e10 vcc e11 gca0/io93ndb1 e12 io94ndb1 f1 gfb0/io208npb3 f2 vcomplf f3 gfb1/io208ppb3 f4 io206npb3 f5 gnd f6 gnd f7 gnd f8 gcc0/io91ndb1 f9 gcb0/io92npb1 f10 gnd f11 gca1/io93pdb1 f12 gca2/io94pdb1 144-pin fbga pin number a3p1000 function g1 gfa1/io207ppb3 g2 gnd g3 vccplf g4 gfa0/io207npb3 g5 gnd g6 gnd g7 gnd g8 gdc1/io111ppb1 g9 io96ndb1 g10 gcc2/io96pdb1 g11 io95ndb1 g12 gcb2/io95pdb1 h1 vcc h2 gfb2/io205pdb3 h3 gfc2/io204psb3 h4 gec1/io190pdb3 h5 vcc h6 io105pdb1 h7 io105ndb1 h8 gdb2/io115rsb2 h9 gdc0/io111npb1 h10 vccib1 h11 io101psb1 h12 vcc j1 geb1/io189pdb3 j2 io205ndb3 j3 vccib3 j4 gec0/io190ndb3 j5 io160rsb2 j6 io157rsb2 j7 vcc j8 tck j9 gda2/io114rsb2 j10 tdo j11 gda1/io113pdb1 j12 gdb1/io112pdb1 144-pin fbga pin number a3p1000 function
automotive proasic3 flash family fpgas revision 1 3-17 k1 geb0/io189ndb3 k2 gea1/io188pdb3 k3 gea0/io188ndb3 k4 gea2/io187rsb2 k5 io169rsb2 k6 io152rsb2 k7 gnd k8 io117rsb2 k9 gdc2/io116rsb2 k10 gnd k11 gda0/io113ndb1 k12 gdb0/io112ndb1 l1 gnd l2 vmv3 l3 geb2/io186rsb2 l4 io172rsb2 l5 vccib2 l6 io153rsb2 l7 io144rsb2 l8 io140rsb2 l9 tms l10 vjtag l11 vmv2 l12 trst m1 gndq m2 gec2/io185rsb2 m3 io173rsb2 m4 io168rsb2 m5 io161rsb2 m6 io156rsb2 m7 io145rsb2 m8 io141rsb2 m9 tdi m10 vccib2 m11 vpump m12 gndq 144-pin fbga pin number a3p1000 function
package pin assignments 3-18 revision 1 256-pin fbga note for package manufacturing and environmental information, visit the resource center at http://www.actel.com/products /solutions/package/docs.aspx . note: this is the bottom view of the package. 1 3 5 7 9 11 13 15 2 4 6 8 10 12 14 16 c e g j l n r d f h k m p t b a a1 ball pad corner
automotive proasic3 flash family fpgas revision 1 3-19 256-pin fbga pin number a3p250 function a1 gnd a2 gaa0/io00rsb0 a3 gaa1/io01rsb0 a4 gab0/io02rsb0 a5 io07rsb0 a6 io10rsb0 a7 io11rsb0 a8 io15rsb0 a9 io20rsb0 a10 io25rsb0 a11 io29rsb0 a12 io33rsb0 a13 gbb1/io38rsb0 a14 gba0/io39rsb0 a15 gba1/io40rsb0 a16 gnd b1 gab2/io117udb3 b2 gaa2/io118udb3 b3 nc b4 gab1/io03rsb0 b5 io06rsb0 b6 io09rsb0 b7 io12rsb0 b8 io16rsb0 b9 io21rsb0 b10 io26rsb0 b11 io30rsb0 b12 gbc1/io36rsb0 b13 gbb0/io37rsb0 b14 nc b15 gba2/io41pdb1 b16 io41ndb1 c1 io117vdb3 c2 io118vdb3 c3 nc c4 nc c5 gac0/io04rsb0 c6 gac1/io05rsb0 c7 io13rsb0 c8 io17rsb0 c9 io22rsb0 c10 io27rsb0 c11 io31rsb0 c12 gbc0/io35rsb0 c13 io34rsb0 c14 nc c15 io42npb1 c16 io44pdb1 d1 io114vdb3 d2 io114udb3 d3 gac2/io116udb3 d4 nc d5 gndq d6 io08rsb0 d7 io14rsb0 d8 io18rsb0 d9 io23rsb0 d10 io28rsb0 d11 io32rsb0 d12 gndq d13 nc d14 gbb2/io42ppb1 d15 nc d16 io44ndb1 e1 io113pdb3 e2 nc e3 io116vdb3 e4 io115udb3 e5 vmv0 e6 v cci b0 e7 v cci b0 e8 io19rsb0 256-pin fbga pin number a3p250 function e9 io24rsb0 e10 v cci b0 e11 v cci b0 e12 vmv1 e13 gbc2/io43pdb1 e14 io46rsb1 e15 nc e16 io45pdb1 f1 io113ndb3 f2 io112ppb3 f3 nc f4 io115vdb3 f5 v cci b3 f6 gnd f7 v cc f8 v cc f9 v cc f10 v cc f11 gnd f12 v cci b1 f13 io43ndb1 f14 nc f15 io47ppb1 f16 io45ndb1 g1 io111ndb3 g2 io111pdb3 g3 io112npb3 g4 gfc1/io110ppb3 g5 v cci b3 g6 v cc g7 gnd g8 gnd g9 gnd g10 gnd g11 v cc g12 v cci b1 256-pin fbga pin number a3p250 function
package pin assignments 3-20 revision 1 g13 gcc1/io48ppb1 g14 io47npb1 g15 io54pdb1 g16 io54ndb1 h1 gfb0/io109npb3 h2 gfa0/io108ndb3 h3 gfb1/io109ppb3 h4 v complf h5 gfc0/io110npb3 h6 v cc h7 gnd h8 gnd h9 gnd h10 gnd h11 v cc h12 gcc0/io48npb1 h13 gcb1/io49ppb1 h14 gca0/io50npb1 h15 nc h16 gcb0/io49npb1 j1 gfa2/io107ppb3 j2 gfa1/io108pdb3 j3 v ccplf j4 io106ndb3 j5 gfb2/io106pdb3 j6 v cc j7 gnd j8 gnd j9 gnd j10 gnd j11 v cc j12 gcb2/io52ppb1 j13 gca1/io50ppb1 j14 gcc2/io53ppb1 j15 nc j16 gca2/io51pdb1 256-pin fbga pin number a3p250 function k1 gfc2/io105pdb3 k2 io107npb3 k3 io104ppb3 k4 nc k5 v cci b3 k6 v cc k7 gnd k8 gnd k9 gnd k10 gnd k11 v cc k12 v cci b1 k13 io52npb1 k14 io55rsb1 k15 io53npb1 k16 io51ndb1 l1 io105ndb3 l2 io104npb3 l3 nc l4 io102rsb3 l5 v cci b3 l6 gnd l7 v cc l8 v cc l9 v cc l10 v cc l11 gnd l12 v cci b1 l13 gdb0/io59vpb1 l14 io57vdb1 l15 io57udb1 l16 io56pdb1 m1 io103pdb3 m2 nc m3 io101npb3 m4 gec0/io100npb3 256-pin fbga pin number a3p250 function m5 vmv3 m6 v cci b2 m7 v cci b2 m8 nc m9 io74rsb2 m10 v cci b2 m11 v cci b2 m12 vmv2 m13 nc m14 gdb1/io59upb1 m15 gdc1/io58udb1 m16 io56ndb1 n1 io103ndb3 n2 io101ppb3 n3 gec1/io100ppb3 n4 nc n5 gndq n6 gea2/io97rsb2 n7 io86rsb2 n8 io82rsb2 n9 io75rsb2 n10 io69rsb2 n11 io64rsb2 n12 gndq n13 nc n14 v jtag n15 gdc0/io58vdb1 n16 gda1/io60udb1 p1 geb1/io99pdb3 p2 geb0/io99ndb3 p3 nc p4 nc p5 io92rsb2 p6 io89rsb2 p7 io85rsb2 p8 io81rsb2 256-pin fbga pin number a3p250 function
automotive proasic3 flash family fpgas revision 1 3-21 p9 io76rsb2 p10 io71rsb2 p11 io66rsb2 p12 nc p13 tck p14 v pump p15 trst p16 gda0/io60vdb1 r1 gea1/io98pdb3 r2 gea0/io98ndb3 r3 nc r4 gec2/io95rsb2 r5 io91rsb2 r6 io88rsb2 r7 io84rsb2 r8 io80rsb2 r9 io77rsb2 r10 io72rsb2 r11 io68rsb2 r12 io65rsb2 r13 gdb2/io62rsb2 r14 tdi r15 nc r16 tdo t1 gnd t2 io94rsb2 t3 geb2/io96rsb2 t4 io93rsb2 t5 io90rsb2 t6 io87rsb2 t7 io83rsb2 t8 io79rsb2 t9 io78rsb2 t10 io73rsb2 t11 io70rsb2 t12 gdc2/io63rsb2 256-pin fbga pin number a3p250 function t13 io67rsb2 t14 gda2/io61rsb2 t15 tms t16 gnd 256-pin fbga pin number a3p250 function
package pin assignments 3-22 revision 1 256-pin fbga pin number a3p1000 function a1 gnd a2 gaa0/io00rsb0 a3 gaa1/io01rsb0 a4 gab0/io02rsb0 a5 io16rsb0 a6 io22rsb0 a7 io28rsb0 a8 io35rsb0 a9 io45rsb0 a10 io50rsb0 a11 io55rsb0 a12 io61rsb0 a13 gbb1/io75rsb0 a14 gba0/io76rsb0 a15 gba1/io77rsb0 a16 gnd b1 gab2/io224pdb3 b2 gaa2/io225pdb3 b3 gndq b4 gab1/io03rsb0 b5 io17rsb0 b6 io21rsb0 b7 io27rsb0 b8 io34rsb0 b9 io44rsb0 b10 io51rsb0 b11 io57rsb0 b12 gbc1/io73rsb0 b13 gbb0/io74rsb0 b14 io71rsb0 b15 gba2/io78pdb1 b16 io81pdb1 c1 io224ndb3 c2 io225ndb3 c3 vmv3 c4 io11rsb0 c5 gac0/io04rsb0 c6 gac1/io05rsb0 c7 io25rsb0 c8 io36rsb0 c9 io42rsb0 c10 io49rsb0 c11 io56rsb0 c12 gbc0/io72rsb0 c13 io62rsb0 c14 vmv0 c15 io78ndb1 c16 io81ndb1 d1 io222ndb3 d2 io222pdb3 d3 gac2/io223pdb3 d4 io223ndb3 d5 gndq d6 io23rsb0 d7 io29rsb0 d8 io33rsb0 d9 io46rsb0 d10 io52rsb0 d11 io60rsb0 d12 gndq d13 io80ndb1 d14 gbb2/io79pdb1 d15 io79ndb1 d16 io82nsb1 e1 io217pdb3 e2 io218pdb3 e3 io221ndb3 e4 io221pdb3 e5 vmv0 e6 v cci b0 e7 v cci b0 e8 io38rsb0 256-pin fbga pin number a3p1000 function e9 io47rsb0 e10 v cci b0 e11 v cci b0 e12 vmv1 e13 gbc2/io80pdb1 e14 io83ppb1 e15 io86ppb1 e16 io87pdb1 f1 io217ndb3 f2 io218ndb3 f3 io216pdb3 f4 io216ndb3 f5 v cci b3 f6 gnd f7 v cc f8 v cc f9 v cc f10 v cc f11 gnd f12 v cci b1 f13 io83npb1 f14 io86npb1 f15 io90ppb1 f16 io87ndb1 g1 io210psb3 g2 io213ndb3 g3 io213pdb3 g4 gfc1/io209ppb3 g5 v cci b3 g6 v cc g7 gnd g8 gnd g9 gnd g10 gnd g11 v cc g12 v cci b1 256-pin fbga pin number a3p1000 function
automotive proasic3 flash family fpgas revision 1 3-23 g13 gcc1/io91ppb1 g14 io90npb1 g15 io88pdb1 g16 io88ndb1 h1 gfb0/io208npb3 h2 gfa0/io207ndb3 h3 gfb1/io208ppb3 h4 v complf h5 gfc0/io209npb3 h6 v cc h7 gnd h8 gnd h9 gnd h10 gnd h11 v cc h12 gcc0/io91npb1 h13 gcb1/io92ppb1 h14 gca0/io93npb1 h15 io96npb1 h16 gcb0/io92npb1 j1 gfa2/io206psb3 j2 gfa1/io207pdb3 j3 v ccplf j4 io205ndb3 j5 gfb2/io205pdb3 j6 v cc j7 gnd j8 gnd j9 gnd j10 gnd j11 v cc j12 gcb2/io95ppb1 j13 gca1/io93ppb1 j14 gcc2/io96ppb1 j15 io100ppb1 j16 gca2/io94psb1 256-pin fbga pin number a3p1000 function k1 gfc2/io204pdb3 k2 io204ndb3 k3 io203ndb3 k4 io203pdb3 k5 v cci b3 k6 v cc k7 gnd k8 gnd k9 gnd k10 gnd k11 v cc k12 v cci b1 k13 io95npb1 k14 io100npb1 k15 io102ndb1 k16 io102pdb1 l1 io202ndb3 l2 io202pdb3 l3 io196ppb3 l4 io193ppb3 l5 v cci b3 l6 gnd l7 v cc l8 v cc l9 v cc l10 v cc l11 gnd l12 v cci b1 l13 gdb0/io112npb1 l14 io106ndb1 l15 io106pdb1 l16 io107pdb1 m1 io197nsb3 m2 io196npb3 m3 io193npb3 m4 gec0/io190npb3 256-pin fbga pin number a3p1000 function m5 vmv3 m6 v cci b2 m7 v cci b2 m8 io147rsb2 m9 io136rsb2 m10 v cci b2 m11 v cci b2 m12 vmv2 m13 io110ndb1 m14 gdb1/io112ppb1 m15 gdc1/io111pdb1 m16 io107ndb1 n1 io194psb3 n2 io192ppb3 n3 gec1/io190ppb3 n4 io192npb3 n5 gndq n6 gea2/io187rsb2 n7 io161rsb2 n8 io155rsb2 n9 io141rsb2 n10 io129rsb2 n11 io124rsb2 n12 gndq n13 io110pdb1 n14 v jtag n15 gdc0/io111ndb1 n16 gda1/io113pdb1 p1 geb1/io189pdb3 p2 geb0/io189ndb3 p3 vmv2 p4 io179rsb2 p5 io171rsb2 p6 io165rsb2 p7 io159rsb2 p8 io151rsb2 256-pin fbga pin number a3p1000 function
package pin assignments 3-24 revision 1 p9 io137rsb2 p10 io134rsb2 p11 io128rsb2 p12 vmv1 p13 tck p14 v pump p15 trst p16 gda0/io113ndb1 r1 gea1/io188pdb3 r2 gea0/io188ndb3 r3 io184rsb2 r4 gec2/io185rsb2 r5 io168rsb2 r6 io163rsb2 r7 io157rsb2 r8 io149rsb2 r9 io143rsb2 r10 io138rsb2 r11 io131rsb2 r12 io125rsb2 r13 gdb2/io115rsb2 r14 tdi r15 gndq r16 tdo t1 gnd t2 io183rsb2 t3 geb2/io186rsb2 t4 io172rsb2 t5 io170rsb2 t6 io164rsb2 t7 io158rsb2 t8 io153rsb2 t9 io142rsb2 t10 io135rsb2 t11 io130rsb2 t12 gdc2/io116rsb2 256-pin fbga pin number a3p1000 function t13 io120rsb2 t14 gda2/io114rsb2 t15 tms t16 gnd 256-pin fbga pin number a3p1000 function
automotive proasic3 flash family fpgas revision 1 3-25 484-pin fbga note for package manufacturing and environmental information, visit the resource center at http://www.actel.com/products /solutions/package/docs.aspx . note: this is the bottom view of the package. a b c d e f g h j k l m n p r t u v w y aa ab 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 a1 ball pad corner
package pin assignments 3-26 revision 1 484-pin fbga* pin number a3p1000 function a1 gnd a2 gnd a3 v cci b0 a4 io07rsb0 a5 io09rsb0 a6 io13rsb0 a7 io18rsb0 a8 io20rsb0 a9 io26rsb0 a10 io32rsb0 a11 io40rsb0 a12 io41rsb0 a13 io53rsb0 a14 io59rsb0 a15 io64rsb0 a16 io65rsb0 a17 io67rsb0 a18 io69rsb0 a19 nc a20 v cci b0 a21 gnd a22 gnd b1 gnd b2 v cci b3 b3 nc b4 io06rsb0 b5 io08rsb0 b6 io12rsb0 b7 io15rsb0 b8 io19rsb0 b9 io24rsb0 b10 io31rsb0 b11 io39rsb0 b12 io48rsb0 b13 io54rsb0 b14 io58rsb0 b15 io63rsb0 b16 io66rsb0 b17 io68rsb0 b18 io70rsb0 b19 nc b20 nc b21 v cci b1 b22 gnd c1 v cci b3 c2 io220pdb3 c3 nc c4 nc c5 gnd c6 io10rsb0 c7 io14rsb0 c8 v cc c9 v cc c10 io30rsb0 c11 io37rsb0 c12 io43rsb0 c13 nc c14 v cc c15 v cc c16 nc c17 nc c18 gnd c19 nc c20 nc c21 nc c22 v cci b1 d1 io219pdb3 d2 io220ndb3 d3 nc d4 gnd d5 gaa0/io00rsb0 d6 gaa1/io01rsb0 484-pin fbga* pin number a3p1000 function d7 gab0/io02rsb0 d8 io16rsb0 d9 io22rsb0 d10 io28rsb0 d11 io35rsb0 d12 io45rsb0 d13 io50rsb0 d14 io55rsb0 d15 io61rsb0 d16 gbb1/io75rsb0 d17 gba0/io76rsb0 d18 gba1/io77rsb0 d19 gnd d20 nc d21 nc d22 nc e1 io219ndb3 e2 nc e3 gnd e4 gab2/io224pdb3 e5 gaa2/io225pdb3 e6 gndq e7 gab1/io03rsb0 e8 io17rsb0 e9 io21rsb0 e10 io27rsb0 e11 io34rsb0 e12 io44rsb0 e13 io51rsb0 e14 io57rsb0 e15 gbc1/io73rsb0 e16 gbb0/io74rsb0 e17 io71rsb0 e18 gba2/io78pdb1 e19 io81pdb1 e20 gnd 484-pin fbga* pin number a3p1000 function
automotive proasic3 flash family fpgas revision 1 3-27 e21 nc e22 io84pdb1 f1 nc f2 io215pdb3 f3 io215ndb3 f4 io224ndb3 f5 io225ndb3 f6 vmv3 f7 io11rsb0 f8 gac0/io04rsb0 f9 gac1/io05rsb0 f10 io25rsb0 f11 io36rsb0 f12 io42rsb0 f13 io49rsb0 f14 io56rsb0 f15 gbc0/io72rsb0 f16 io62rsb0 f17 vmv0 f18 io78ndb1 f19 io81ndb1 f20 io82ppb1 f21 nc f22 io84ndb1 g1 io214ndb3 g2 io214pdb3 g3 nc g4 io222ndb3 g5 io222pdb3 g6 gac2/io223pdb3 g7 io223ndb3 g8 gndq g9 io23rsb0 g10 io29rsb0 g11 io33rsb0 g12 io46rsb0 484-pin fbga* pin number a3p1000 function g13 io52rsb0 g14 io60rsb0 g15 gndq g16 io80ndb1 g17 gbb2/io79pdb1 g18 io79ndb1 g19 io82npb1 g20 io85pdb1 g21 io85ndb1 g22 nc h1 nc h2 nc h3 v cc h4 io217pdb3 h5 io218pdb3 h6 io221ndb3 h7 io221pdb3 h8 vmv0 h9 v cci b0 h10 v cci b0 h11 io38rsb0 h12 io47rsb0 h13 v cci b0 h14 v cci b0 h15 vmv1 h16 gbc2/io80pdb1 h17 io83ppb1 h18 io86ppb1 h19 io87pdb1 h20 v cc h21 nc h22 nc j1 io212ndb3 j2 io212pdb3 j3 nc j4 io217ndb3 484-pin fbga* pin number a3p1000 function j5 io218ndb3 j6 io216pdb3 j7 io216ndb3 j8 v cci b3 j9 gnd j10 v cc j11 v cc j12 v cc j13 v cc j14 gnd j15 v cci b1 j16 io83npb1 j17 io86npb1 j18 io90ppb1 j19 io87ndb1 j20 nc j21 io89pdb1 j22 io89ndb1 k1 io211pdb3 k2 io211ndb3 k3 nc k4 io210ppb3 k5 io213ndb3 k6 io213pdb3 k7 gfc1/io209ppb3 k8 v cci b3 k9 v cc k10 gnd k11 gnd k12 gnd k13 gnd k14 v cc k15 v cci b1 k16 gcc1/io91ppb1 k17 io90npb1 k18 io88pdb1 484-pin fbga* pin number a3p1000 function
package pin assignments 3-28 revision 1 k19 io88ndb1 k20 io94npb1 k21 io98ndb1 k22 io98pdb1 l1 nc l2 io200pdb3 l3 io210npb3 l4 gfb0/io208npb3 l5 gfa0/io207ndb3 l6 gfb1/io208ppb3 l7 v complf l8 gfc0/io209npb3 l9 v cc l10 gnd l11 gnd l12 gnd l13 gnd l14 v cc l15 gcc0/io91npb1 l16 gcb1/io92ppb1 l17 gca0/io93npb1 l18 io96npb1 l19 gcb0/io92npb1 l20 io97pdb1 l21 io97ndb1 l22 io99npb1 m1 nc m2 io200ndb3 m3 io206ndb3 m4 gfa2/io206pdb3 m5 gfa1/io207pdb3 m6 v ccplf m7 io205ndb3 m8 gfb2/io205pdb3 m9 v cc m10 gnd 484-pin fbga* pin number a3p1000 function m11 gnd m12 gnd m13 gnd m14 v cc m15 gcb2/io95ppb1 m16 gca1/io93ppb1 m17 gcc2/io96ppb1 m18 io100ppb1 m19 gca2/io94ppb1 m20 io101ppb1 m21 io99ppb1 m22 nc n1 io201ndb3 n2 io201pdb3 n3 nc n4 gfc2/io204pdb3 n5 io204ndb3 n6 io203ndb3 n7 io203pdb3 n8 v cci b3 n9 v cc n10 gnd n11 gnd n12 gnd n13 gnd n14 v cc n15 v cci b1 n16 io95npb1 n17 io100npb1 n18 io102ndb1 n19 io102pdb1 n20 nc n21 io101npb1 n22 io103pdb1 p1 nc p2 io199pdb3 484-pin fbga* pin number a3p1000 function p3 io199ndb3 p4 io202ndb3 p5 io202pdb3 p6 io196ppb3 p7 io193ppb3 p8 v cci b3 p9 gnd p10 v cc p11 v cc p12 v cc p13 v cc p14 gnd p15 v cci b1 p16 gdb0/io112npb1 p17 io106ndb1 p18 io106pdb1 p19 io107pdb1 p20 nc p21 io104pdb1 p22 io103ndb1 r1 nc r2 io197ppb3 r3 v cc r4 io197npb3 r5 io196npb3 r6 io193npb3 r7 gec0/io190npb3 r8 vmv3 r9 v cci b2 r10 v cci b2 r11 io147rsb2 r12 io136rsb2 r13 v cci b2 r14 v cci b2 r15 vmv2 r16 io110ndb1 484-pin fbga* pin number a3p1000 function
automotive proasic3 flash family fpgas revision 1 3-29 r17 gdb1/io112ppb1 r18 gdc1/io111pdb1 r19 io107ndb1 r20 v cc r21 io104ndb1 r22 io105pdb1 t1 io198pdb3 t2 io198ndb3 t3 nc t4 io194ppb3 t5 io192ppb3 t6 gec1/io190ppb3 t7 io192npb3 t8 gndq t9 gea2/io187rsb2 t10 io161rsb2 t11 io155rsb2 t12 io141rsb2 t13 io129rsb2 t14 io124rsb2 t15 gndq t16 io110pdb1 t17 v jtag t18 gdc0/io111ndb1 t19 gda1/io113pdb1 t20 nc t21 io108pdb1 t22 io105ndb1 u1 io195pdb3 u2 io195ndb3 u3 io194npb3 u4 geb1/io189pdb3 u5 geb0/io189ndb3 u6 vmv2 u7 io179rsb2 u8 io171rsb2 484-pin fbga* pin number a3p1000 function u9 io165rsb2 u10 io159rsb2 u11 io151rsb2 u12 io137rsb2 u13 io134rsb2 u14 io128rsb2 u15 vmv1 u16 tck u17 v pump u18 trst u19 gda0/io113ndb1 u20 nc u21 io108ndb1 u22 io109pdb1 v1 nc v2 nc v3 gnd v4 gea1/io188pdb3 v5 gea0/io188ndb3 v6 io184rsb2 v7 gec2/io185rsb2 v8 io168rsb2 v9 io163rsb2 v10 io157rsb2 v11 io149rsb2 v12 io143rsb2 v13 io138rsb2 v14 io131rsb2 v15 io125rsb2 v16 gdb2/io115rsb2 v17 tdi v18 gndq v19 tdo v20 gnd v21 nc v22 io109ndb1 484-pin fbga* pin number a3p1000 function w1 nc w2 io191pdb3 w3 nc w4 gnd w5 io183rsb2 w6 geb2/io186rsb2 w7 io172rsb2 w8 io170rsb2 w9 io164rsb2 w10 io158rsb2 w11 io153rsb2 w12 io142rsb2 w13 io135rsb2 w14 io130rsb2 w15 gdc2/io116rsb2 w16 io120rsb2 w17 gda2/io114rsb2 w18 tms w19 gnd w20 nc w21 nc w22 nc y1 v cci b3 y2 io191ndb3 y3 nc y4 io182rsb2 y5 gnd y6 io177rsb2 y7 io174rsb2 y8 v cc y9 v cc y10 io154rsb2 y11 io148rsb2 y12 io140rsb2 y13 nc y14 v cc 484-pin fbga* pin number a3p1000 function
package pin assignments 3-30 revision 1 y15 v cc y16 nc y17 nc y18 gnd y19 nc y20 nc y21 nc y22 v cci b1 aa1 gnd aa2 v cci b3 aa3 nc aa4 io181rsb2 aa5 io178rsb2 aa6 io175rsb2 aa7 io169rsb2 aa8 io166rsb2 aa9 io160rsb2 aa10 io152rsb2 aa11 io146rsb2 aa12 io139rsb2 aa13 io133rsb2 aa14 nc aa15 nc aa16 io122rsb2 aa17 io119rsb2 aa18 io117rsb2 aa19 nc aa20 nc aa21 v cci b1 aa22 gnd ab1 gnd ab2 gnd ab3 v cci b2 ab4 io180rsb2 ab5 io176rsb2 ab6 io173rsb2 484-pin fbga* pin number a3p1000 function ab7 io167rsb2 ab8 io162rsb2 ab9 io156rsb2 ab10 io150rsb2 ab11 io145rsb2 ab12 io144rsb2 ab13 io132rsb2 ab14 io127rsb2 ab15 io126rsb2 ab16 io123rsb2 ab17 io121rsb2 ab18 io118rsb2 ab19 nc ab20 v cci b2 ab21 gnd ab22 gnd 484-pin fbga* pin number a3p1000 function
revision 1 4-1 4 ? datasheet information list of changes the following table lists critical changes that were made in each revision of the automotive proasic3 datasheet. revision changes page july 2010 the versioning system for datasheets has been changed. datasheets are assigned a revision number that increm ents each time the datasheet is revised. the "automotive proasic3 device status" table on page ii indicates the status for each device in the device family. n/a revision 1 (dec 2009) product brief v1.1 the qng132 package was added to the "automotive proasic3 product family" table , "i/os per package" table , "automotive proasic3 ordering information" , and "temperature grade offerings" . i ? iv packaging v1.1 pin tables for a3p125 and a3p250 were added for the "132-pin qfn" package. 3-5
datasheet information 4-2 revision 1 datasheet categories categories in order to provide the latest information to des igners, some datasheet parameters are published before data has been fully characterized from silicon devices. the data provided for a given device, as highlighted in the "automotive proasic3 device status" table on page ii , is designated as either "product brief," "advance," "preliminary," or "production." th e definitions of these categories are as follows: product brief the product brief is a summarized version of a data sheet (advance or producti on) and contains general product information. this document gives an overvi ew of specific device and family information. advance this version contains initial estimated information bas ed on simulation, other products, devices, or speed grades. this information can be used as estimates, bu t not for production. this label only applies to the dc and switching characteristics chapter of the da tasheet and will only be used when the data has not been fully characterized. preliminary the datasheet contains information based on simulation and/or initial characterization. the information is believed to be correct, but changes are possible. unmarked (production) this version contains information that is considered to be final. export administration regulations (ear) the products described in this document are subj ect to the export administ ration regulations (ear). they could require an approved export license prior to export from the united st ates. an export includes release of product or disclosure of technology to a foreign national inside or outside the united states. actel safety critical, life support, and high-reliability applications policy the actel products described in this advance status document may not have completed actel?s qualification process. actel may amend or enhanc e products during the pr oduct introduction and qualification process, resulting in changes in device functionality or performance. it is the responsibility of each customer to ensure the fitness of any actel pr oduct (but especially a new product) for a particular purpose, including appropriateness for safety-critical, life-support, and other high-reliability applications. consult actel?s terms and conditions for specific liab ility exclusions relating to life-support applications. a reliability report covering all of actel?s products is available on the actel website at http://www.actel.com/documents/ort_report.pdf . actel also offers a variety of enhanced qualification and lot acceptance screening procedures. contact your local actel sales office for additional reliability information.

actel is the leader in low power fpgas and mixed signal fpgas and offers the most comprehensive portfolio of system and power management solutions. power matters. learn more at www.actel.com. actel corporation 2061 stierlin court mountain view, ca 94043-4655 usa phone 650.318.4200 fax 650.318.4600 actel europe ltd. river court,meadows business park station approach, blackwater camberley surrey gu17 9ab united kingdom phone +44 (0) 1276 609 300 fax +44 (0) 1276 607 540 actel japan exos ebisu buillding 4f 1-24-14 ebisu shibuya-ku tokyo 150 japan phone +81.03.3445.7671 fax +81.03.3445.7668 http://jp.actel.com actel hong kong room 2107, china resources building 26 harbour road wanchai, hong kong phone +852 2185 6460 fax +852 2185 6488 www.actel.com.cn 51700099-1/12.09 ? actel corporation. all rights reserved. actel, actel fusion, igloo, libero, pigeon point, pro asic, smartfusion and the associ ated logos are trademarks or registered trademarks of actel corporation. all other trademarks and service marks are the property of their resp ective owners.

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